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Recent content by michaelScott

  1. M

    How to connect AXI_LITE port of QSPI_FLASH to the RISC-V processor.

    Hello friends. I want to load an application from SPI flash into DDR memory and starts application running in DDR memory i.e. bootloader. However QSPI_FLASH has an AXI_LITE input but RISCV processor has not. So how can I connect QSPI_FLASH to the RISCV processor. Thanks in advance
  2. M

    Matlab train vehicle coding

    Hello friends, I want to model a train on MATLAB and i want to observe the vibration arising from the train displacement velocity and from the acceleration. For modelling the train I used quarter rail vehicle model as seen on the picture below. Also the equations of motion can be seen below. The...
  3. M

    Port width mismatch SIMULINK

    Hello friends, While i was coding matlab function module i get an error message as seen below which gives a port mismatch error. Can you help me on coding. ERROR MESSAGE: Port width mismatch. Input 'u' expects a signal of size 1. The signal received is of size 6.
  4. M

    [SOLVED] Quarter rail vehicle model

    Hello friends, I want to implement a rail vehicle model on the MATLAB/SIMULINK. Quarter rail vehicle model is shown as below The equations of motion are also obtained as below. Can you please explain how to derive the equations. Can you help me to implement this on MATLAB as the scheme below
  5. M

    Resampling scaling truncating Matlab data file

    I need to perform the conditions to the data file below on the matlab. can you help me how to do that. Data File = 2x460800 Conditions: 1.) The scaling defined in the PhysioNet .info files for each PhysioNet data file was applied to each raw data file. 2.) The data were resampled to a common...
  6. M

    [SOLVED] Process exited with value 3221225477

    Hello friends, I am currently working on a homework. But the code i wrote is not works as expected what i mean is that when i run the code sometimes i get the following error and integer values get unreasonable values. Where do i do wrong. Can you help me. Thanks in advance #include <stdio.h>...
  7. M

    Missing design modules on testbench error

    Hello friends, While simulating a design wrapper file. I am getting a error messages as seen below. Despite all the modules names are correct in the wrapper file Why i am getting these errors. Can you help me about that. Thanks i advance
  8. M

    [SOLVED] RISC-V Register File

    thanks. i was careless i did not notice
  9. M

    [SOLVED] RISC-V Register File

    Hello friends, I am designing a register file which is compatible with RISC-V ISA definitions. But as seen on the simulation result register does not read the data input despite the RTL schematic shows no problem. Can you help me about that. Thanks in advance. the codes...
  10. M

    RISCV ALU Specifications

    thanks for the reply, so we perform arithmetical, logical, compare, jump&link operations in the ALU right?
  11. M

    RISCV ALU Specifications

    Hello people, I am designing an ALU for RISCV processor and i wonder if i need to perform compare and branches instructions inside the alu. thanks in advance
  12. M

    [SOLVED] VERILOG Unknown Output value

    Thank you very much. I solved the problem
  13. M

    [SOLVED] VERILOG Unknown Output value

    Hello friends, In my verilog code as you can see despite that i am able to see correct result in carrylookahead module, in the top module shows output as unknown value. What is the reason for that what coding i do wrong. Thanks in advance. `timescale 1ns / 1ps module alu( input [31:0] X...
  14. M

    [SOLVED] ALU Design on VIVADO for RISCV Architecture

    Hello people, I am designing a RISCV ALU on VIVADO and i want all the instructions as sub-blocks as seen the code below(carry-lookahead adder/subtractor). I want only one carry-lookahead adder/subtractor in the ALU for the different instructions like add and subtract. Can you help me about...
  15. M

    ZYNQ-7000(XC7Z035 FFG676) Device Model in VIVADO

    Hello friends, i have a FPGA Development Board which contains XC7Z035 FFG676 chip. To work on this project i obtained VIVADO 2017.4 HL Design Edition but it needs license to work on HL Design Edition. I downloaded Webpack Edition(free) but it does not support XC7Z035 FFG676 chip. Can you help...
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