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Hello friends,
While simulating a design wrapper file. I am getting a error messages as seen below. Despite all the modules names are correct in the wrapper file Why i am getting these errors. Can you help me about that.
Thanks i advance
@michaelScott
1. It is typical Xilinx IDE, you should have posted this in the FPGA forum! Please take care about such stuff in the future.
2. This design has some kind of a BRAM which needs to be generated as a Xilinx IP, this is missing.
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