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you need to first compile the verilog file with :
vlogan verilog_tb.v
then elaboration:
vcs tb (the library not file name)
simulation:
./simv
check out the vcs_mx users guide
is it possible to load the SDF file during simulation ?
for example in the testbench
initial begin
wait(top.i_dut.i_module.signal === 1'b1)
$sdf_annotat(...);
end
change
import "DPI-C" string_sv2c=task string_sv2c();
to
import "DPI-C" string_sv2c=function void string_sv2c();
(you don't have to rename the function and I think it's better to move the import declaration out of the program)
for files string_sv2c.sv & string_sv2c.c
run :
vlib...
You need to import the function in your sv code:
import "DPI" function int get_pid();
import "DPI" function int get_vmem( output string output_str_ptr );
Questasim will compile c files with vlog so you need to just add the files in your "do" file
I am not familiar with the GPIO UVC but it seems that the test shuts down after zero time.
The first thing to check is do you have a sequence, have you connected it to the GPIO sequencer and does
the sequence raise an objection until it finishes the body
clocking block is useful for verification environments where you have
one task driving the signals and another sampling them.
If a clocking block isn't used and the signals are driven and sampled on the same clk edge
the signals could be sampled before they are driven (depends on how the...
for uvm you have to add the option +ntb_opts uvm so the comand will look something like :
vcs -sverilog +ntb_opts uvm <your files>
in 1 of your files you also have to add :
import uvm_pkg::*;
`include "uvm_macros.svh"
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