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Re: clock gating
The only automatic tool i know of that can fix the timing on gate-level clock gating is Azuro's PowrCentric (www.azuro.com).
Of course, you can't fix clock gate timing at the RTL level. All you can do in the RTL is force the clock gates way down the tree where they drive only...
dcreddy1980 is correct. Each library has its own drive strengths. The x-factors are more comparative than absolute. I don't think you should interpret them too literally.
Re: Clock gating ?
Hi Mouzid:
The big problem with clock gates that you absolutely have to verify is that in the logical space the clock signal is "ideal". This means that it magiacally shows up at all the clock pins at the same time.
In a real circuit, you have to synthesize a clock tree to...
Re: why scan chain is deleted before placement and reconnect
No, the scan chain is still required before placement because the ATPG test coverage tools require it to generate their test vectors. Test coverage is usually determined before waiting for final placement. The bit order of these...
logic drive strength capability
Every gate can adequately drive a certain maximum capacitive load (wire cap + input pin cap). By 'adequately' is meant that the signal will not exceed the maximum rise time. Having a signal transition too slowly is bad for many reasons (excessive power, strong...
Re: Clock gating ?
Yes, logically it is equivalent to clock gating. There are however 2 points you need to check before you decide it works:
1. Where does the control signal come from? Is it generated from flops driven by the 50MHz clock you are switching off? Are you sure the control...
No, scan chain reordering doesn't change the names of the registers or pins. Think about it - how could timing exceptions still be valid if all the FF names changed? How could you know what the new scan order was if all the names were changed?
The names don't change.
Re: Clock gating ?
No, the circuit shows a divider, not clock gating.
Clock gating is a low-power technique whereby you switch off certain branches of the clock tree when that part of the logic is not needed. This saves a lot of power by preventing needles switching of those FFs and clock...
The whole question is a bit spurious. Who on earth cares what the vaguely defined marketing term "gate count" is? Gate count is not used in any serious discussions on the nature of a chip.
If you want to know how 'big' a design is - i.e.: what manufacturing effort was required, you quote the...
Azuro's PowerCentric will give you a dynamic and leakage power analysis. You can supply a VCD, but you don't need to with their vectorless activity generation. It's not free though.
An important point all the previous respondents failed to mention is that your simulation must be representative...
asic gates
This analysis is very simplified, but the assumption is that the customer will pay the same for an ASIC or an FPGA implementation. The customer doesn't care how you did it as long as it works according to spec. So the revenue for selling x number of units is the same no matter which...
It depends on your design style - bottom-up or top-down.
In a bottom-up design style (which is the most common) you are designing the block before you design the top-level that assembles the blocks. In this case you have no information on the signal delay outside the block because it has not...
Hi:
I apologize for being a bit too brief in my first posting. You are really worried about two problems: Not exceeding the maximum current density and not exceeding the maximum voltage-drop limit. The power ring must be sized so as to satisfy both these requirements.
Both problems require...
Noise does affect current. Depending on the rest of the circuit, this current may, or may not, lead to a significant voltage change.
Let's look at the three basic mechanisms involved in noise as it occurs in ICs:
(a) Capacitive coupling between signal wires:
This is the dominant noise effect...
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