drive strength of a gate

[ASIC_intl]

drive strength and rise time

When it is said 0x drive, 1x drive. What does it mean?

Does it mean driving capability interms of a basic gate? What is the basic gate then? What is the exact driving capability of that basic gate?
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[MarcS]

logic drive strength capability

Every gate can adequately drive a certain maximum capacitive load (wire cap + input pin cap). By 'adequately' is meant that the signal will not exceed the maximum rise time. Having a signal transition too slowly is bad for many reasons (excessive power, strong possibility of crosstalk), but the most immediately relevant one is that the library timing has been characterized assuming the slew rate is at least a certain minimum. If you drop below that, then none of your library timing numbers are correct anymore.

In any case, every cell has a maximum load it can drive. A 'X2' cell is logically identical, but can drive more load than a 'X1' version. An a X4 can drive even more, and so on. The trade-off is that the higher drive cells are significantly larger than the weaker drive cells. So you only use the high-drive cells where you need to.

 

[ASIC_intl]

increase the cap increase the drive strength

The explanation is nice. But I need to know the meaning of x in 1x, 2x. while we talk of drive strength. What is the exact driving capability of a gate when its dive strngth is 2x? It may mean that it can drive twice than a gate whose drive strength is 1x. Then what is the actual value of the gate whose drive strength is 1x?

 

[dcreddy1980]

figuring out drive strength for a gate

what is the actual value of the gate whose drive strength is 1x? --> Each technology library has different values, please open up ur library file and u can find it out for all the cells.

 

[ytliang]

I think those mean the fan-out of the gate. It indicates its ability to drive the number of inputs of other logic gates of the same type

 

[MarcS]

dcreddy1980 is correct. Each library has its own drive strengths. The x-factors are more comparative than absolute. I don't think you should interpret them too literally.

 

[ASIC_intl]

In the library x (of 1x) is not defined.

Suppose in the library I found an an AND2 gate whose inputs has fanout_load of 0.74 and 0.82.
What does this fanout_load mean?