How to get the gate count after synthesis?

[johnli100]

synthesize basic gate

How to get the gate count number after synthesis? How to estimate the raft die size?

 

[jbeniston]

synthesis area gate count

Which synthesis tool are you using?

Try report_area or report area

If you just get an area (not gate count), divide the area by the area of a 2-input NAND gate (basic drive strength)

 

[ASIC_intl]

gate count

Hi jbeniston

2-input NAND gate is not always the basic gate probably. Are you sure that in your library 2 input nand is the basic nand gate? Which library are you using?

 

[Nir Dahan]

the NAND 2 equivalent is the basic measure unit in which area is compared.
regardless if it is the basic gate or not.
it is just A WAY we can all have a common language when discussing size.
think of it as a way to normalize the given quantity in terms of gates.

IMHO jbeniston is correct

ND
https://asicdigitaldesign.wordpress.com

 

[ASIC_intl]

Hi

Few days ago there was a similar discussion. IN that discussion it was discussed out that an inverter is the basic unit cell. Even in library you will find inverter having area as 0.9 or less than 1.

Added after 11 minutes:

Is it generally true that NAND2 is always the basic cell for unit area in libraies of all fabrication foundries?

There are many NAND2 gates in a library with different areas. T
What is the basic unit cell for calculating area among all these NAND2 of different areas?

How can I know the exact value of the area of the basic gate?
When it is said 0x drive, 1x drive. What does it mean?

Does it mean driving capability interms of a basic gate? What is the basic gate then? What is the exact driving capability of that basic gate?

 

[jbeniston]

Few days ago there was a similar discussion. IN that discussion it was discussed out that an inverter is the basic unit cell. Even in library you will find inverter having area as 0.9 or less than 1.

Area is typically in um^2, not relative to a particular cell.

When it is said 0x drive, 1x drive. What does it mean?

It is the drive strength of the cell - the higher the drive strength, the larger the load it can drive.

 

[ashy]

Nand2 is used as a general circuit for calculating Gate count, Possible reasons are
1) Nand is a universal gate
You can ask NOR is also a universal gate so why not nand gate, it is well known that although you can use both NAND or NOR to get any other logic , NAND is more commonly used because it has a lower logical effort when compared to a NOR gate.
logical effort is a indication of the logical complexity of a gate with respect a standard inverter.

 

[MarcS]

The whole question is a bit spurious. Who on earth cares what the vaguely defined marketing term "gate count" is? Gate count is not used in any serious discussions on the nature of a chip.

If you want to know how 'big' a design is - i.e.: what manufacturing effort was required, you quote the number of transistors and/or the total die area.

If you want to know how complex a design is you quote the number of placeable instances. This reflects how hard it was to design.

For example; a large RAM block on the chip represents an impressive transistor count that requires good processing technology to reliably manufacture. But from a design perspective it is trivial - it is only one component from the designer's point of view. Gate count sheds no light on the matter.

 

[ASIC_intl]

Hi jbeniston

What is it implied by um^2 ?

 

[dcreddy1980]

um^2 --> square microns