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hi
as colin said we use self-aligned process while fabricating th CMOS.in this, poly will be used as mask layer as it is deposited first then implantation for diffusions is carried out. The reason why poly is deposited first is, here we get exact length of the poly.but if we do it the other...
Re: Happy New Year
I Wish You A Very Happy and Prosperous New Year....
hope the industry will get settle down and we have good time in the future :D manjula
Hi ...
here goes my question...i am reading about substrate noise coupling..
i found something like
lightley doped substrate will be highley resistive and noise attenuation will be better.
and reverse is the case for highly doped substrate. like
highly doped substrate ---> less resistive--->...
u have to use metal 1 or 2 , if u want to connect in metal 5,6.
the starting metal is M1. routing from S,D will have to start from M1 only..
Gate u will connect thru poly ,M1 contact.
after it is depend on the requirement. if they r carrying higher currents and u want to reduce the resistance...
snap-spacing
Hi all,
plz dont think that it is a stupid questions.
what happens if w dont follow the grid and snap spacing while doing laying out the devices.
will there be any impact while fabricating?????
Re: Poly layer Route
hi
it depends on foundry...in tSMC u need not to cover poly with any implants.make sure that it is less resistive...that can be possible by placing more contacts rather than 2 and covering the poly with metal 1.
but again ..when u come to oter foundry...u have to coverthe...
Re: its about ERC..
Thank u all....
i dont want to connect using diffusion layers....my doubt is what happens if its get connected thru diffusion...and one more is as far as my knowledge diffusion layers are less resistive not highly resistive.....is it so?????
in my idea...ERC will check for soft checks....soft checks means routing through a nonroutable layer.example for nourouting layers are diffusions.the question is why are not we supposed to use these layers for routing????
metal chips density
consider you have got waiver for the density or you have ignored it or u r DRC does not check u r density ...meaning u have a separate check for density....
what happens if you did not meet the required denisty.that means you have the density less than the required. what...
density of all metals
hi.... i have one more question here....
why do we fix the desity at full chip level to a max and min value.
what happens if i have the metal density(%) greater than the maximum(%).
HI,
somebody asked me about Impedense matching.
i have heard of device matching and resistor matching.
but dont know what is ipmedense matching in doing layouts.
can somebody help me ????
thanks
manruru
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