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I could not remember how to spell but the pronouciation is like "leaf"
a format from the back-end process.
Who know that is it?
Help...
Added after 2 minutes:
It is used in back annotated information.... not "LEF"
VCS 7.0 ( or some version like that ) or higher becomes what is called NTB ( Native testbench builder ). It integrate the Vera, system verilog, Direct C ...
U could build you testbench by these more powerful languages...
It is a state-of-art process.
You know what is best. But you will have to reach a local optimal.
What is local optimal? It depends the resource available, the market requirement and also quality guideline.
Added after 4 minutes:
It is a state-of-art process.
You know what is best. But you...
sdram controller tutorial
the controller has a digital dll inside,and the dll can be tune by some programble parammeter to get the delay you want.
but how should I choose the appropriate delay?before physical place&route and board route,I can't get the right delay I want.
The DLL should be...
Memory arbiter
round-robin arbiter is same as others...
MUX bank, the select pin is controlled by your control logic, comb or seq, depending on your timing budget and timing reqirement. In your case, often a count and some comb logic for the control logic.
Draw a timing diagram you get it.
powerplanning concepts of asic
Different technologies are different. Read the design rule document from the foundry there will be the sugestion.
In most cases, it is hard to estimate the current on the power ring when you are routing. Make it as conservative as possible..
Re: verilog program
Yes, I have read the book. It teaches you to write verilog in a high level way. Many data stucture like class are taught.
Not bad.
But Verilog is still very limited in behavioral description. Vera, or System Verilog is better...
Are you writing a behavioral description? If so, what ever you are doing is ok.
If you are designing a circuit, ... ... ...
The first thing you need to do is DESCRIBE it in ENGLISH.
ddr timing diagrams
To make it simple, let's descibe in the following way.
First, you will have a clear specification in your DDR controller interface. The timing diagram specified the frequency, duty cycle, setup, hold time etc, in most cases, with max and min in a range.
Then, you convert...
OCV
CLOCK TREE LEVELS is the level of hirachies of the leaf trees. And in each clock tree level, there are serveral clock buffers.
For example, in the layout, you have two seperate block in the same clock domain. You could design your clock in such a way that the top level of the clock tree...
It is hard to simply say which one is "good"...
Usually if your design is not the extreme case it is hard to evaluate the performance of the tool simply by better...
But in the real design enviroment, you always know which one is "better" since the design flow will not be changed easily in...
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