How to run architecture 256 times in verilog(it is very urge

[ravindra kalla]

hi,

I have code an architecture in verilog.I want to run this architecture 256 times,how can i do this.If i put always are any loop then i can not call architecture inside this.SO please tell me how can i run architecture 256 times.

it is very urgent for me.

 

[echo47]

Sorry, parts of your question are unintelligible. Please rewrite.

Run an architecture??

Do you want 256 copies of the same logic, so they execute in parallel? Two common way to do that: use a "for" loop, or use a "generate" block (available in Verilog 2001).

Do you want to do some operation 256 times in sequence? You can use a counter that triggers your operation 256 times.

If you tell us a simple example of what you want to accomplish, maybe someone can help you better.

 

[ravindra kalla]

Re: How to run architecture 256 times in verilog(it is very

yes i want to trigger architecture 256 times so that some operation can perform sequentialy.

please reply soon

 

[sean_111]

Re: How to run architecture 256 times in verilog(it is very

give it a series of vectors contain 256 pattens.

 

[luancao]

Are you writing a behavioral description? If so, what ever you are doing is ok.

If you are designing a circuit, ... ... ...
The first thing you need to do is DESCRIBE it in ENGLISH.

 

[jimjim2k]

Re: How to run architecture 256 times in verilog(it is very

yes i want to trigger architecture 256 times so that some operation can perform sequentialy.

please reply soon

Hi

Use verilog IEEE's std 2001 "generate" feature.


tnx

 

[echo47]

Re: How to run architecture 256 times in verilog(it is very

I still don't fully understand your question, but maybe this simple example will help you.

The "start" input pulse begins a sequence of 256 "trigger" pulses. Each "trigger" pulse begins a sequence of three "out" pulses.

module top (clk, start, out);
  input             clk, start;
  reg        [11:0] count = 0;
  reg               trigger = 0;
  reg         [4:0] sr = 0;
  output reg        out = 0;

  always @ (posedge clk) begin
    // When "start" pulse received, generate 256 "trigger" pulses
    count <= count + (start | (count != 0));
    trigger <= count[3:0] == 1;

    // When "trigger" pulse received, generate 3 "out" pulses
    sr <= {sr,trigger};
    out <= sr[4] | sr[2] | sr[0];
  end
endmodule