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Recent content by liujingshu

  1. L

    About EEPROM Cell current

    Hi,everyone, I was asked design a charge pump for eeprom. I choose the four phase clock architecture of charge pump, and the function is ok. But I am not sure the program(or erase) current of the eeprom cell after the charge up voltage is 15.5v, some one say is 10uA, and some one say is...
  2. L

    What is the meaning of postplace opt with propagate clocks?

    About the clock tree Hi,guy, What is the meaning of postplace opt with propagate clocks, how to do it??
  3. L

    How to pick the data from different frequencies in Verilog?

    How to pick the data How to pick the data from different frequencies in the verilog. I mean, for example, if the high frequecy means 1, and the low frequecy means 0, and how to actualize in the verilog code. Thanks
  4. L

    Hold time problem with Verilog netlist

    hold time problem I think this problem should me ignored. Thanks your reply
  5. L

    Hold time problem with Verilog netlist

    hold time problem Hi,guy, My verilog netlist have hold time problem, but this problem happen at the very begining even before the reset signal, at the time the code still unwork. Do you think I have to fix this problem?
  6. L

    What is a good core utilization percent ?

    Core utilization Hi, guy My chip's core utilization only 81%. Does it meaning very bad?
  7. L

    Need documents about Clock Tree Synthesis

    Clock Tree Synthesis Thank you so much for your document.
  8. L

    How to build a memory hard macro for Astro

    Thank you very much for you reply
  9. L

    Ask a question about clock tree

    Hi,guy I want to ask a question about clock tree. If clock2 is divide by clock1 which is the port clock, and how to clock tree synthesis about the clock2??
  10. L

    Tips for test benches????

    I think one thing you should do is understand clearly what is you design
  11. L

    How to build a memory hard macro for Astro

    Now I p&R a design, and this design have memory IP core, but I don't know how to build a memory hard macro for Astro. Can anyone give me any tips. Thanks.
  12. L

    About verilog compile

    Thank you very much! But I can't understand what's the meaning of "separate combinational and sequential parts based on Huff-man model ", can you give me some explanation, I am still a new code writer. I find there are so many counter in this module, I doubt the problem is here.
  13. L

    How to synchronize the two clocks running at different freq?

    Re: How to synchronize the two clocks running at different f My experience is you shoulde constrate on the code. You should stagger the two clocks.
  14. L

    About verilog compile

    verilog compiler explanation Hi,all Our company assign me to stimulate(use Modelsim) and compile(use Design compiler) a code. The stimulation is not very difficult, but compiled is not easy, for it is my first compile job. I can say the code is not very good, for most of module can pass the...
  15. L

    Basic questions about gate level net list

    Re: Gate level net list You can use the sdf file to back annotate the gate netlist. There will be timing
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