What is the meaning of postplace opt with propagate clocks?

[liujingshu]

About the clock tree

Hi,guy,
What is the meaning of postplace opt with propagate clocks, how to do it??

 

[eda_wiz]

About the clock tree

During initial synthesis the actual values of clock insertion delay , clock transition time etc are not known. so during prelayout synthesis we use d commands , set_clock_transition ,set_clock_latency to model the clock tree .

Once you insert the clock tree, the actual values of these parameters can be calculated by DC/PT. For that we ask the tool to propagate the clock through the clock tree and find these values.

its done by using set_propagated_clock


hope it helps

 

[funster]

Re: About the clock tree

clock tree synthesis and optimization is done

by P&R tools collectively after floorplan is finished.

you needn't worry about it.

best regards

Hi,guy,
What is the meaning of postplace opt with propagate clocks, how to do it??