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Recent content by linkfox

  1. L

    XTAL1 capacitance of Pierce oscillator

    Good to find this post, we also met similar problem recently and resolved it by enlarging the Xtal1 cap.
  2. L

    Anyone know how to take DVI/HDMI and get parallel RGB values

    Re: Anyone know how to take DVI/HDMI and get parallel RGB va this is called input processor or receiver. u can check with silicon image or ADI, as I remember, SiL9025, 9125, 9135 can do this work
  3. L

    HOW TO IMPLEMENET FOLLOWING EQ. IN VHDL

    vhdl calculation of percentage you can find implementations for fixed point divisions on-line, on FPGA they provided division IP cores; but they can only return quotient and remainder, but not 0.5 as u want; so my suggest would be either do a1 = (total expected pulses/255), then (no. of pulses...
  4. L

    need a matlab code to computer for throughput

    Re: MATLAB CODE these can ealisy be related to some kind of IP or patent issues, not the amount that u can afford, i affraid.
  5. L

    Two stage folded cascode amplifier?

    improve the output voltage swing and reduce the output impedance (thus keep the gain when there is external load)
  6. L

    Differential output in cadence

    draw the amplifier into some unity-gain configuration, then out~input, and you can check the max.input.range
  7. L

    need MATLAB m-file on Generate pseudo-random binary sequence

    generate m sequence you can try LFSR, the diagram and its C code can be found in https://en.wikipedia.org/wiki/Linear_feedback_shift_register
  8. L

    how to make ring oscillator work well

    I guess you are asking how to start the "oscillation" in Cadence, then this link can be help: **broken link removed** page down and you will see the initial setting also, the gain is >1, and phase shift should be (2N+1)Pi instead of 2Pi
  9. L

    In analog design how to deal with temperature compensation.

    Re: In analog design how to deal with temperature compensati bandgap reference is a good example
  10. L

    I have got a baby girl

    congratulations!!
  11. L

    array variable index in VHDL ?

    vhdl index pieces from one code: ... use ieee.std_logic_arith.all; .... Write_Addr: in std_logic_vector(addr-1 downto 0); .... type ram_type is array (0 to depth-1) of std_logic_vector(width-1 downto 0); signal tmp_ram: ram_type; .... tmp_ram(conv_integer(Write_Addr)) <= Data_in;
  12. L

    Suggestions needed for a FPGA board

    < $150?? three years our group bought a DN6000 board with 6 virtex-2p from it, the price is $40K.
  13. L

    Why does metal2 shold be vertical ?

    No, it is not necessary. I think this kind of layout is to reduce the magnetic interference and crosstalk between two kinds of metals

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