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Thank you very much! I use the @ltera APEX KE familay FPGAs. Does APEX 20KE familiy support this feature? If it cannot be done in the APEX 20KE FPGAs, which FPGAs provided by @ltera do support adjusting the pll on the fly?
:o
I my project, the clock frequency of circuit need be adjusted on the fly! So, I am looking for an approach to control the pll on real time!
Thank you in advance!:)
FPGA Power
As what I know, there are not commercial behavior level power estimation tools now! So your design described by C code cannot be used for power estimation. You must implement your design in netlist fashion first.
FPGA Power
If you want to get the clear breakdown of power consumption of your design, you can use the power estimation tool that provides by Xilinx ISE, called XPower.
In my point of view, using counter is a good choice! How to implement the FSM depends on your favariate. The most important thing is that FSM must synchronize with the incoming bitstream.
error:hdlparsers:808 read file
The conversion function to_bit() in the std_logic_1164 package can not apply to the boolean type operand. You can overload it to implement what you want.
Is there any vendor support the function of switching off unused resource of FPGA devices! If it works, the static power of the circuits implemented in FPGA will reduce greatly.
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