Is there any way to control the pll of the FPGA on the fly?

[leonyang]

I my project, the clock frequency of circuit need be adjusted on the fly! So, I am looking for an approach to control the pll on real time!
Thank you in advance!

 

[Black Jack]

Re: Is there any way to control the pll of the FPGA on the f

What part are you use?
ACTEL`s ProASIC PLUS have this features (via JTAG)

But if you use PLL for frequency synthesys
(not for data synch.) see DDS
(Direct Digital Synthesys)

 

[silencer3]

depending on ethe device you use, this can be done or not. In any case it is difficult to do. i never tried. Actel proasic supports this

 

[leonyang]

Thank you very much! I use the @ltera APEX KE familay FPGAs. Does APEX 20KE familiy support this feature? If it cannot be done in the APEX 20KE FPGAs, which FPGAs provided by @ltera do support adjusting the pll on the fly?

 

[cawan]

The pll in fpga need to be preconfigured and can't be controlled on the fly. As what we know, the pll configuration is perform through the wizard and the wizard will generate the appropriate hdl code. The hdl code need to be recompile or synthesis, place and route to get the sof file. I think the only way that can make pll be controlled on the fly is compile multiple of sof and keep in different partition in flash. Use a flash controller to configure the fpga with defferent set of sof file may be can meet your requirement.

 

[dewdrop]

i think the pll can not be control at work,but you can use the counter to control the frequency of the pll output.

 

[dragon_boat]

i think u can generate different frequency output inside,but control by interface or switch outside.

 

[Aser]

Re: Is there any way to control the pll of the FPGA on the f

You can do the outer clock oscillator as VCO.
This VCO can be controlled by a simple analog circuit of DAC, for instance based on the RC integrator which is loaded by impulses.
These impulses are generated by the loop net designed in FPGA, which compares the the precise clock with the VCO frequency divided by the given coefficient.

 

[power-twq]

Re: Is there any way to control the pll of the FPGA on the f

When pll's setting is changed, The pll's output clock will not

change into new frequency immediately. you should take

this instability into account.

best regards

I my project, the clock frequency of circuit need be adjusted on the fly! So, I am looking for an approach to control the pll on real time!
Thank you in advance!

 

[jarodz]

Hi leonyang,

The PLL of Stratix device provided by Altera can be reconfigured on the fly. And it is very easy to be controlled. May it be helpful to you.

Regards,
Jarod