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Recent content by leonken

  1. L

    high supply voltage amplifer made by low and high voltage mosfet?

    Does there any paper related to this topic? high supply voltage, cmos folded-cascade amplifer made by low voltage mosfet and high voltage mosfet both. thanks.
  2. L

    Any paper about low voltage input diff pair used in the high volage amp?

    Any papers about this issue: high supply voltage but low voltage input diff pair is used in order to reduce size and to improve the matching issue. Thanks.
  3. L

    How to determine the slew rate of error amplifier for DCDC converter

    A voltage mode DCDC converter, need to know the slew rate of error amplifer, assume the compensation cap of the error amplifer is C1 and C2, the sawtooth voltage range is 2V. How to calculate the slew rate of error amplifer? thanks.
  4. L

    Any ideas about oneshot OSC with jitter?

    I want to design an OSC with +/- 3% jitter OSC is relized by an schmitt trigger with R and C. The range of jitter is +/- 3%. Any idea about this circuit? Thanks.
  5. L

    How to converter 400Vdc to 5Vdc

    A converter: Input is 400Vdc, output is 5Vdc, load is about 100uA. How to realize this circuit in IC design? Thanks.
  6. L

    Need help: several uS one-shot circuit for DCDC converter

    one shot circuit Does anyone can upload some documents about a one shot circuit for DC DC converter design. One shot circuit is used to generate several micro second period for dcdc covverter applcation. Thanks.
  7. L

    How does this VCO work?

    How this VCO works? How to tune the frequency? How the gate voltage of M3 and M4 is controlled by M5 and M6 and Vcont?
  8. L

    Are there any differences between PSR and PSRR?

    Are there any differences between PSR and PSRR? Thanks.
  9. L

    How to realize a freq. triple circuit ?

    The duty cycle of the input pulse signal is variable and is very small. The duty cycle of the output of PLL is fixed...
  10. L

    How to realize a freq. triple circuit ?

    How to realize a circuit that its output pulse freqeuency is 3 or 4 times larger than the input pulse frequency? Please see the attached figure. Thanks [/img]
  11. L

    question on low drop out regulator

    Because the Vdd(Vin) of the opamp is supplied by Vin. The output of opamp is less than Vdd(Vin).
  12. L

    question on low drop out regulator

    Two kind of regulators: NMOS pass device and PMOS pass device. Why the voltage drop across the pass deivce of PMOS is smaller than the NMOS? Added after 37 minutes: The figure
  13. L

    Help: How this VCO works?

    The author metioned in his paper: the M5 and M6 are used to control the maximum gate voltage of M3 and M4. I do not know how to realize it?
  14. L

    Help: How this VCO works?

    How this VCO works? How to tune the frequency? The gate voltage of M3 and M4 is controlled by M5 and M6 and Vcont. When vout+ or vout- is Vdd , does M5 or M6 acts as a voltage follow( common drain scheme) to control the gate voltage of M3 or M4 alternatively?
  15. L

    who knows the locking time of PLL for various applications?

    I'm a beginner for PLL. In general, the locking time (lock time) of PLL for different application is different. Where can I found the summary of locking times for different application. Thank you.
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