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Why reset active low ??
because in popular DFF's design, the set or reset circuit is implemented by nand gate. If the reset or set is active high, we have to use nor gate or at least add one inverter for these signals.
Nor gate have worse performance compared nand gate (for same area) since...
verilog mux
1. one (if) has priority the other(case) has no
2. case have full/parallel concept
3. no impact to remove the default since the case is full case
4. possible mismatch in gatelevel and rtl simulation.
I dont think clock wire should be routed at the top metal. In large scale of design, clock tree is often needed and will not restricted it to use only top metal.
clock latency
basically, the clock latency is the delay from the clock root pin (clock source) to the clock leaf pin (such as clock pin of a DFF). Different clock leaf pin may have different latency, which is clock skew.
In design, during pre-layout, you will need to set the clock latency you...
except for timing and DFT issues, Latch based design is often easy make circuit fail. This will need carefully designed and balanced for each path delay.
One example is that Latch is easy to cause combinational loop back and easy to cause osc effects. Often latch based circuit is using two...
active low may be quick to be asserted. The signal change from high to low is through NMOS transistor, which have better driving strength than PMOS.
this technique is often used in memory array.
You design does not seem have timing issues and I am afraid the congestion problem caused the routing fails.
80% Utilization is too low in most of the case, but it depends on how big of your design. If your design exceed millions of gates. You may need to change your floorplanning to reduce the...
1. what is your row utilization?
2. have you opened the timing driving routing?
3. have you analyzed the congestion issue?
4. did you get very serious timing violation before APR?
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