DC synthesis question ?

[mediatek]

synopsys sync_set_reset

if I need a DFF with async_set and async_reset
always@(posedge clk or negedge zrst or posedge sset)

when I use
//synopsys one_hot "zrst,sset"
always@(posedge clk or negedge zrst or posedge sset)
....
to synthesis
and not use it then synthesis,
always@(posedge clk or negedge zrst or posedge sset)
....
I check the two synthesis result
find the netlist is the same ?
WHY??????????????????????????????????????????????????

how to know //synopsys full_case one_hot ............
is working( from synthesis log file or .....)
?

 

[tony_taoyh]

sync_set_reset

What type is used for this DFF in your generated netlist?

Thanks.

 

[kxchorus]

synopsys async_set_reset

It will depends on what kind of DFF in your library which will meet the RTL.

 

[laobian]

synopsys design compiler set posedge set negedge

Normally，one system just has only one RESET signal connect to the CLR or SET pin of DFF, not both of them. So, the result alway is the same.

 

[roger]

dc synthesis reset

check your .lib file and search if there exist a reset/set DFF

 

[Thomson]

dff with synchronous reset and set

First check your library to make sure that it includes such type of registers;
Second, the following may help:
The Verilog attributes for set and reset are:

// synopsys async_set_reset
// synopsys sync_set_reset
// synopsys async_set_reset_local
// synopsys sync_set_reset_local
// synopsys async_set_reset_local_all
// synopsys sync_set_reset_local_all


Sample Verilog code to infer a synchronous set flip-flop and a synchronous reset flip-flop:
----------------------------------------------------------------------------------------

module sync_set_reset(clk, reset, set, d1, d2, y, t) ;
input clk, reset, set, d1, d2 ;
output y, t ;
// synopsys sync_set_reset "reset, set"
reg y, t ;
always @ (posedge clk)
begin : synchronous_reset
if (reset)
y = 1'b0; // synchronous reset
else
y = d1;
end
always @ (posedge clk)
begin : synchronous_set
if (set)
t = 1'b1; // synchronous set
else
t = d2;
end
endmodule


Verifying that the attributes were correctly applied
----------------------------------------------------

Before you read the HDL code, set the Design Compiler variable

hdlin_report_inferred_modules = verbose

to get a complete inference report of the sequential cells. After you
read in the HDL, check the inference report to see that the attributes
were correctly applied.

Third to make sure that if it's necessary to contain the asynchronous reset&set simultaneously in the same module. In effect, it's not easy to conduct the static timing analysis with regards to the asynchronous feature of the signal. If you have good experience of asynchronous reset, then you'd better to avoid such coding style. Only including the aynchronous reset is allowed and recommended in your coding, especially avoiding the usage of internal asynchronous signals since it's difficult for the analysis of testing and timing.

 

[sunms]

dc synthesis

Hi guy,
It depends on the lib you used.
Make sue if it support reset and set function, or just only set or reset.