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Recent content by kuntul

  1. K

    fastest way to compare numbers

    and how do I do that in xilinx?
  2. K

    fastest way to compare numbers

    What is the fastest possible way to compare two 32 bit numbers? As of now I am using verilog '==' and when I synthesize it the delays are enormous.
  3. K

    synthesis and simulation different behavior

    Okay... finally after a few hours I managed to find the problem. In my code I use '=' instead of a '<=' when assigning registers and therefore when running synthesis the register got all trimmed out and it behaves differently. Now here's to the main problem, if I need to use '<=' because I...
  4. K

    synthesis and simulation different behavior

    please let me know on how to do this: basic gate sim with timing with the implementation netlist.
  5. K

    synthesis and simulation different behavior

    I am using iSim. I do believe that the branch module I have above is not the problem as I've removed that and still does the same thing
  6. K

    problem with always block and sensitivity list

    you mean I need to change it so that the sensitivity list is EXMEMrd...etc,etc...
  7. K

    problem with always block and sensitivity list

    I don't see any logic problem there..... what are you seeing?
  8. K

    problem with always block and sensitivity list

    I have a verilog code below. always @(posedge Clk) begin ForwardA = 0; ForwardB = 0; //EX Hazard if (EXMEMRegWrite == 1) begin if (EXMEMrd != 0) if (EXMEMrd == IDEXrs) ForwardA = 2'b10; if (EXMEMrd == IDEXrt && IDEXTest == 0) ForwardB = 2'b10; end //MEM Hazard if...
  9. K

    synthesis and simulation different behavior

    I have written a mips pipelined datapath using verilog and then it does what it's supposed to do on simulation (ISim), however when I run synthesis and put it on my FPGA board it behaves differently. I have a branch instruction which branches when it's not supposed to, however on simulation...
  10. K

    behavior vs gate level code

    so when synthesizing the speedup I get from using gate level and say verilog code, result 1 + result 2 is the same as xilinx will optimize it for us?
  11. K

    behavior vs gate level code

    so if I use Result1 + Result2 in verilog and on synthesis xilinx won't translate that to a carry lookahead gate adder? or any faster gate level addition?
  12. K

    CLOCK_SIGNAL constraint

    I am getting the following warning in my synthesis report: I have a combinatorial logic that takes the Clk from the board and slows it down by a factor of 1250, basically a clock divider. Based from reading the manual in verilog I have put the following code in my top module: // synthesis...
  13. K

    behavior vs gate level code

    if I choose one over the other then does it affect on the speedup I will gain on the synthesis report?
  14. K

    behavior vs gate level code

    I am implementing a single cycle datapath in verilog and it has an ALU inside of it. One of the ALU functionality is to add.. and I did use the verilog '+' sign for this. If I had another module to perform add using gate level, will this make my clock speed much faster when I synthesize? The...
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