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network_latency_included
if only max input delay is set, what happened to hold check for the path from the primary input ?
1. does PT defaults max input delay to min input delay ?
2. does PT defaults 0 to min input delay ?
3. does PT unconstrain the input port for hold check ?
thanks!!!
Regardless of whether to use it or not, I have a code that contains huge internal tristate bus, and almost for sure I have(or wish) to reuse the entire code. In RTL, there is a specific Pullup verilog keyword to drive the bus high when tristate buffer is disabled.
Does DC understand this...
I have a design where data is about a clock late in post layout sim, compared to RTL. This data is supposed to be latched with latch_enable(not flopped), which is pretty much matching RTL behavior. Hence, the data to be latched is arriving about a clock(reference clock) late compared to enable...
Hi,
I am learning timing analysis, and came to this question. would appreciate if you can confirm my thought/learning. thanks.
since
Thold <= Tmindelay + Tclktoq,
I concluded that Thold requirement does not influence operating frequency at all. Is this correct ?
:oops:
I do think...
i have a path violating su.
Looking at the netlist, it must be false because the path for some reasons bypass the flops that are supposed to in between the start and end points.
I mean my understanding of false path was those related to reset or path in asyncrounous/multi clock boundaries...
sorry not an answer to your question.
But you might get more replies from analog board.
Nothing wrong with posting, I dont think. Just a suggestion.
ksl
Not if you want full rail to rail output. Fets would stop conducting before output reach Vss or Vdd. The source of NFET needs to be Vssed for full swing down to Vss , and the source of PFET needs to be Vdded for full swing upto Vdd. I forgot the exact formula, but it is in electronic books...
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