kslim
Newbie level 5
I have a design where data is about a clock late in post layout sim, compared to RTL. This data is supposed to be latched with latch_enable(not flopped), which is pretty much matching RTL behavior. Hence, the data to be latched is arriving about a clock(reference clock) late compared to enable signal.
Easy fix would be shift the latch_enable by a clock, but I am not sure this would guerantee correct timing in real silicon. Is this a proper method to fix the problem ? Are there more "proper" methods to fix this ? Thanks.
Easy fix would be shift the latch_enable by a clock, but I am not sure this would guerantee correct timing in real silicon. Is this a proper method to fix the problem ? Are there more "proper" methods to fix this ? Thanks.