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how do you time latch enable ?

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kslim

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I have a design where data is about a clock late in post layout sim, compared to RTL. This data is supposed to be latched with latch_enable(not flopped), which is pretty much matching RTL behavior. Hence, the data to be latched is arriving about a clock(reference clock) late compared to enable signal.

Easy fix would be shift the latch_enable by a clock, but I am not sure this would guerantee correct timing in real silicon. Is this a proper method to fix the problem ? Are there more "proper" methods to fix this ? Thanks.
 

Generally you should not let go off such a problem lightly.

One thing is that you have to look at the extra clock delay that you insert for the latching signal from a higher viewpoint. Does it cause a problem with overall functionality that the data is now onme clock delayed?

The other thing to investigate is to find the delay in the min case. Will it cause a hold violation if you shift the latch enable by one clock?
- b
 

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