a false path in striclty 1 clock syncronous rtl possible ?

[kslim]

i have a path violating su.
Looking at the netlist, it must be false because the path for some reasons bypass the flops that are supposed to in between the start and end points.

I mean my understanding of false path was those related to reset or path in asyncrounous/multi clock boundaries. The path I am looking at isnt anything involving asynchronous nor reset nor multi clocks.
Thanks for you input.

 

[utmseng]

Re: a false path in striclty 1 clock syncronous rtl possible

STA will analyze all the timing path. As long as there is a logic connection from start point to end point (regardless going through the flop), the STA tool will analyze the path.

So, for path which you think will not be asserted, you can always set_fase_path. The false path is not limited multi clock or reset only.

 

[eeeraghu]

Re: a false path in striclty 1 clock syncronous rtl possible

False Path's should be analyzed by the designers from the critical path and should be given as a constrain to the STA tool, so that it does not checks, thereby providing fast results from the critical paths.

regards
Raghu

 

[anjali]

Re: a false path in striclty 1 clock syncronous rtl possible

false path means the path never have dat flow, according to your logic. then we can constraint that as false path to avoid timing analysis in that path.

 

[dr_dft]

Re: a false path in striclty 1 clock syncronous rtl possible

False path in a single clock domain is definitely possible. One example is a circuit with 2 modes of operation that is mutually exclusive. There could be physical paths between logic from one mode to another, which is not a logical path.
One common example is test modes. For example, when BIST is running, you may not care about paths starting from your BIST controller and flowing into your functional logic and vice versa.
Of course, false paths need to be very carefully reviewed by the designers to see there were some unintended logic. One common cause of this is cut-and-paste errors, in which a designer forgets to modify a signal name after a cut-and-paste, and suddenly an undesirable path pops up.