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Recent content by kshitij_s81

  1. K

    who have met this problem when synthesizing?

    Hi U may have got this problem because u havent specified the wireload model correctly. This problem appears majorly during static timing analysis wherein the tool says that the path is unconstrained even though u might have constrained the design. So u check whether u have correctly specified...
  2. K

    Does anybody have Design Compiler tutorial

    design compiler tutorial Hi friends Does anybody have DC tutorials or lab manuals. If it could had been with an example it would had been nice. Please help us out. Waiting for your reply. Kshitij Sukhwal
  3. K

    How to replace designware cells in the netlist

    Hi friends The problem faced by me is like this My design is meeting the timing when i run synthesis from DC . It does not show me -ve slack But when I do Static Timing Analysis by PT its showing me -ve slack. So somebody suggested me to change the DW components to a faster one but i dont know...
  4. K

    How to replace designware cells in the netlist

    designware cells If the design does not meet constraints how can we change the designware cells in the netlist obtained from DC
  5. K

    How to find the gate count

    U can count the total no of cells in DC by sourcing the total cell file and then running the command DC_rpt_cell
  6. K

    what caused that ... In Design compiler and Why?

    U can use the set_link_library and link all the synthetic libraries as said by our friend and give the link of the synthetic libraries in your set_search_path
  7. K

    how to insert delay buffer?

    Can U help me how to insert buffers into DC and then do STA with PT Waiting for your reply Kshitij Sukhwal
  8. K

    A question about memory and the system speed

    The speed of the system is governed by the following factors 1 processor speed 2 RAM 3 system memory So its not only processor speed or RAM or system memory which alone determines the speed of the process because during the process all the factors like memory management, time management...
  9. K

    Synthesize question about design composed of several modules

    Re: synthesize question We can synthesize the modules by bottom up compile because then we can just characterize the lower sub module and know the environment surrounding the submodule block and hence we can constrain the design more accurately
  10. K

    synopsys design compiler workshop

    Re: primetime workshop lab Hello friends Can Anybody tell me whether this lab material is available on the solvnet site Waiting for your reply Bye Kshitij Sukhwal
  11. K

    how to reduce the slack in dc

    Helllo friends I am new to DC. I would like to know how to reduce slack in the design with the help of DC. Can we replace the designware cells to reduce the critical path and if we can, then how? Please help me out. Bye Kshitij Sukhwal[/u]
  12. K

    PLEASE HELP ME FOR VLSI JOBS IN INDIA

    Hello Friends Well i am doing my post graduate diploma in Embedded systems and VLSI Design from CDAC Noida,India.I am learning VLSI frontend nowadays .Well from the topic "I need a job" i found out some info but was not satisfied from it.I would wish to inquire from users jay_ec_engg and...

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