who have met this problem when synthesizing?

[JesseKing]

after reading rtl code in and full constraining the design, use "check_timing" and i get some endpoints not constrained. but i am quite sure the design was full constrainted with create_clock, input_delay and output_delay.

and after compiling the design and use "check_timing", the not constrained path disappeared!

who can tell me why

best regards

 

[kshitij_s81]

Hi
U may have got this problem because u havent specified the wireload model correctly. This problem appears majorly during static timing analysis wherein the tool says that the path is unconstrained even though u might have constrained the design. So u check whether u have correctly specified the wireload model with its mode.
Regards
Kshitij Sukhwal

 

[spauls]

This is coming because there are signals consumed in more than one clock and you constrainesd them only with one clock, pls check design and use add_delay option .