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Hi folks,
Im new in the RPI environment, I have two RPI3 b model. I would like to configure both of it as an AP and as a wireless client simultaneously. These two RPI3 will connect to each other and exchanging information.Could you pls give me some tutorials about how to do it, I found a lot of...
My PRBS feeds data to psk modulator. in tb for modulator input signal changing with long period and I can observe correct picture today. When I connect PRBS and modulator, input signal (1 and 0) changing quite fast and thats why modulator not able to modulate it. I want to modify my code next...
Hello,
Could you pls give me some hints about PRBS code.My code is working fine.but I would like to modify it. I want that output value will change at leasr after 100ps.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity random is
generic ( width : integer := 5000 );
port (
clock ...
Hello,
I would like to implement simple transmission system between two SDRs(BladeRF). I going to transmit FM signals from one board and receive it on other. Do you have some ideas how to implement this project, or could you pls send me some links on resources where I can check examples who to...
Hello,
I have a project work related with OFDM transmission based on SDR.Im using fft engine from opencores. Maybe someone have mapper for OFDM on vhdl?
I already checked that link/and I know how to convert.My fft engine produce two outputs,each 32 bits width std_logic_vector,after this I want to connect this output whit thransiver input.which has only 16 signed width signal.
Hi,
Could you pls help me,I faced with next problem, I have to signals,one signal is 31 bits width,and the other is 16 bits,how to connect it together?
tx_sample_i : signed(15 downto 0)
s_out : std_logic_vector(31 downto 0)
s_out => tx_sample_i
which conversion should I do?
thanks for reply,I chanched my code/now it works as I want
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
--use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity mapper_2 is
port (
clk,rst : in std_logic;
data_in : in std_logic_vector (2 downto 0)...
i cant simulate it with my device because I have an error like "
Error (119027): Design requires 546 I/O pad resources -- too many to fit in 544 available in the selected device or any device in the device family
Error (119003): Cannot find device that meets Compiler settings specifications...
I want to do mapper for FFT engine (512) so,I have PRSG which generate random data,after this mapper makes mapping of those data which come from PRSG.Data after mapping should looks like (some zeros 1 data 1 data ...1 some zeros)
My device is Cyclone IV E
or mb I dont understand what does it...
so final code looks like this
----mapper
--signal_out[0000001data1data1data.......100000000]
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity mapper_1 is
port (
clk, rst: in std_logic;
data_in : in...
the whole code looks like
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity mapper_1 is
port (
clk, rst: in std_logic;
data_in : in std_logic_vector (3 downto 0);
data_out : out std_logic_vector(27 downto 0)
data_out_1 :out std_logic_vector(2 downto 0)
);
end...
thanks for reply,based on your comments I write my code like this,but I have small question,about if loop,usually the number which mentioned before if (like 8,13,17,21...)they are incremented by 5 every loop until they will reach 512.Could you pls give me some hint or example how can I create...
i have this code but its still not working
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity mapper_1 is
port (
clk: in std_logic;
data_in : in std_logic_vector (9 downto 0);
data_out : out...
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