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Recent content by knataraj

  1. K

    Book for Verilog Synthesis using Synopsys Design Compiler

    verilog synopsys design compiler Hello! I am in need of a Book that teaches me how to code and synthesize Verilog using Synopsys DC. I need something like Weng Fook Lee's VHDL book based on Synopsys. Or if there is some online material or a tutorial that gives me an overview of DC for running...
  2. K

    ASIC Libraries in Cadence

    Hey, I have developed an Ultra low power 32 Bit adder using a new logic style and would like to compare it with a standard CMOS adder. Does Cadence have a built in ASIC libraries like the digitallib in TSMC 0.18u where they have a single bit adder cell designed. I am looking for it because I...
  3. K

    Commands for nested sweep in Cadence

    nested sweep Does anyone know about the commands to run a nested sweep in cadence...I need the netlist commands? I am sweeping the voltage and clock timings. Also...Can we use a variable in setting the tranient analysis stop time? Like if I have a variable "time" can I give the transient...
  4. K

    Parametric Sweep in cadence

    cadence parametric sweep Hi I am using Analog Artist Version 5 and tried to sweep a paramset in spectre. I gave the paramset statement as follows data paramset{ VDC T 0.20 0.6e-06 0.22 1e-06 } swp sweep paramset = data both VDC and T have been defined earlier. When I simulate, I get an...
  5. K

    Parameter Sweep in Cadence

    Hi I am using Analog Artist Version 5 and tried to sweep a paramset in spectre. I gave the paramset statement as follows data paramset{ VDC T 0.20 0.6e-06 0.22 1e-06 } swp sweep paramset = data both VDC and T have been defined earlier. When I simulate, I get an error like: Internal...
  6. K

    Changing the Netlist in Cadence

    Hi , I need to add a save statement in the cadence netlist that will give me a direct plot of power dissipated. If I goto the netlist file and add this statement and run it using the analog artist GUI, the netlist goes back to its original state( save :pwr statement is not saved). Is there any...
  7. K

    Calculating power dissipated and plotting Ids vs time

    Re: Ids plot in cadence Hi Thanks for the Reply! I need the energy dissipated in the Transistor while its conducting. Rather, The energy dissipated in the channel. By Ids, I mean the current flowing in the channel...Id and Is differ and Id and Ib come in to picture too. from what I see, Id or...
  8. K

    Calculating power dissipated and plotting Ids vs time

    plot current versus time cadence Hi people, I need coouple of things related to cadence Schematic/spectre I am using the TSMC 0.18u tech to design and simulate adiabatic circuits(using spectre) 1) Is there any way to calclate the power dissipated in a logic block and get a plot of power vs...

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