Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I am trying to use the barrel shifter provider by the design ware library
so i am using this code which i copied from the examples coming with the library
library IEEE,DWARE,DWARE;
use IEEE.std_logic_1164.all;
use DWARE.DWpackages.all;
use DWARE.DW_foundation_comp.all;
entity...
Thnx
But technology schematic show the look up tables
I want to see the design with all of its buses in the register level
How can i do that ?
And why are certain buses trimmed and other appear ?
in Xilinx ise, when i view the RTL schematic of a module, some buses are connected between the i/o ports and the module and other buses are not connected, what is the reason for this ?
This is an example for what i mean :
Select signal and output are not connected, while the rest is.
I want to build a simple memory module in design compiler
How can I write the VHDL or Verilog code in order for the compiler to build the module using SRAM cells ?
Is there a tutorial or an open source code for a memory module than can be compiled to produce an actual design with SRAM cells ...
I need to implement an on chip multi-port memory in a design
Is there a multi-port memory compiler than can generate a cache with more than 2 ports ?, or do i need to code it myself ?
Thank you for this explanation.
i am just starting to learn ARM so i am running the example programs i find in the book i am learning from
So when i run this code:
AREA Hex_Out,CODE,READONLY
SWI_WriteC EQU &0
SWI_Exit EQU &11
ENTRY
LDR r1, VALUE
BL HexOut
SWI SWI_Exit
VALUE DCD...
I have this line in my code :
MOV PC, r14
It gives an error :
warning: A1608W: MOV pc,<rn> instruction used, but BX <rn> is preferred
So i change it to :
MOV BX, r14
It gave this :
error: A1647E: Bad register name symbol, expected Integer register
help please :)
Vgs = Vg - Vs
so it's the voltage rise from the source to gate
you can say it's like an arrow pointing from S to G
so in the equation you wrote it's Vsg not Vgs , as u pass by G then S on your way from GND to VDD (voltage rise is from gate to source).
I guess that's what you are looking for :
https://www.mathworks.com/help/control/ref/c2d.html
Another simple code is here (if you know the formula of the function)
https://www.edaboard.com/threads/17070/
If your ADC was 10 bit resolution then u can sense a change of 3.3/(2^10) \[\approx\] 3.2 mv so u can represent your signal in 150/3.2 \[\approx\] 47 steps, u can use ADC directly if this step is fine by you, or u can amplify the signal to span the full possible 1024 steps, u can do this by a...
I solved this starting from the loop equation from GND to VDD through VGS, u get VGS = 2ID - 4 , substitute in the ID - VGS relation, get ID and VGS , that should be 0.608 and -2.784 , get VDS from the remaining loop (-6.9) the other value yields VDS < VGS-VTP
Sorry i am new to linux, What i meant was an assembler with GUI interface on ubuntu, Some thing like Code blocks but with an assembler instead of a compiler only.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
