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Recent content by kennyg

  1. K

    How to use SpectreRF to simulate SC-CMFB????

    how to use cmfb Can anyone tell me the procedure or show me the link/tutorial......etc about SC-cmfb simulation? How to simulate common mode Loop gain and phase margin of the ota with SC-cmfb? thanks in advance.
  2. K

    Criterion for ICMR max in opamp of BGR

    ICMR max=vdd-Vov5-(Vthp1+Vov1) ICMR min=vss+(vthn3+Vov3)-vthn1
  3. K

    error in sample hold circuit.who can help me !

    To jnuhope: what's wrong with this closed loop sampling topology from Razavi's book? I can't figure it out.
  4. K

    help impliment this equation in spectre

    In the calculator window, select "Special Functions" -> xval
  5. K

    What's the effect of M2&M3 in this bias circuit

    maybe this is a startup circuit
  6. K

    how to generate timing for SC circuit?

    The schematic which JoannesPaulus post is wrong, Added after 5 minutes: Even numbers of NOT gate follow the NAND,not odd number,AND LOOP doesn't work. Added after 2 minutes: To ricklin: what's your reference for 4 phase nonoverlapping clock design?
  7. K

    advantages of cascode structure..

    Because the gain=gm_input*(1/gm_Cascode) ,this gain is small, so the miller cap=gain*Cgd is small.
  8. K

    How to make Hspice calc caps the same way as Cadence do?

    How to make Hspice calculate parasitic parameters (such as PS PD AS AD RDS RSS SA SB) the same way as Cadence@composer calculate? I think that cadence integrate with the PDK provided by foundry very well, so I trust the parasitic parameter such as AS AD It seem that Hspice calculate the...
  9. K

    how to learn verilogA ?

    Can anyone share the official "Analog Modeling with Verilog-A" Lab manual&Lecture manual?
  10. K

    verilog-a model of 8-to-1 analog mux needed

    veriloga model for mux module mux8to1(in0,in1,in7,out,select) input in0,in1,in7,select; output out; electrical in0,in1,in7,select; real outVal; analog begin case (select) 0:outVal=V(in0); 1:outVal=V(in1); 7:outVal=V(in7); default:outVal=0; endcase V(out)<+outVal; end endmodule Added...
  11. K

    What is the significance of 1.5 bit stage in pipelined ADC?

    Help in pipeline ADC You should get a data converter book and study this elementary concept,or search through this forum first. It's just a redundancy.
  12. K

    Do virtuoso layout lecture&lab manuals exist in this for

    To jiangxb: thanks,but I need the official cadence lecture&lab manuals. thanks anyway.
  13. K

    Do virtuoso layout lecture&lab manuals exist in this for

    layouttutorial.pdf Do virtuoso layout lecture&lab manuals exist in this forum?? Do virtuosoXL lecture&lab manuals exist in this forum?? The userguide and reference manuals is good,but I need a step-by-step tutorial. Thanks in advance!
  14. K

    Print Spectre simulation result to a data file

    spectre save simulation results in file 1.use calculator 2.click "vt" label in calculator panel 3.click "print"labe in calculator panell 4.click the netname in schematic view you want to probe 4 the data show,then "Save As" that's all
  15. K

    What are the advantages of current mirror OTA ?

    Current mirror OTA a paper ("A 0.8V 8-uw,CMOS OTA with 50-dB gain and 1.2-Mhz GBW in 18-pF load") fullfill your needs. Authors:Libin Yao,Willy Sansen.
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