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verilog-a model of 8-to-1 analog mux needed

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analog multiplexer in veriloga

Hello . Can anayone share/ how to program a 8-to-1 analog multiplexer in verilog-a ?

Thx .
 

veriloga model for mux

module mux8to1(in0,in1,in7,out,select)

input in0,in1,in7,select;
output out;
electrical in0,in1,in7,select;
real outVal;

analog begin

case (select)
0:eek:utVal=V(in0);
1:eek:utVal=V(in1);
7:eek:utVal=V(in7);
default:eek:utVal=0;
endcase

V(out)<+outVal;
end

endmodule

Added after 1 minutes:

I don't test this code,please try and give me some feedback advice.
 

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