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Its depends, can be some or all of the following:
- DFT (insert scan, integrate test circuitry ie. BIST, JTAG, improve test coverage)
- ATPG
- Writing test vector
- Write test program
- ASIC test (in tester)
Re: At-speed testing
yes. at-speed test means test the design at its system speed.
Bist test for memory of IP blocks are usally at-speed (they will design to run at system clk speed).
For scan, the at-speed test happens with at-speed launch and capture during scan_enable pin low.
Re: How important is DFT?
For such a small design, you can just write functional vector to test the digital portion, instead of using scan insertion of BIST.
the physical synthesis perform after the floorplan.
however, you can also use phsycal compiler to synthesize the RTL to gates by specifying some "estimated" physical information.
Re: ATPG question
The scan vector is generated by ATPG tool (like tetramax).
The vector (in STIL format) then can be used by the IC tester, to test the chip.
Re: What are the difference between ASIC Verifation and Test
Functional verification - verify the functionality according to the design specification (for example, you check whether 1 + 1 = 2 for adder).
For test, it will check whether the chip have any physical defects (Open, short, ...)...
IC tester apply test patterns in cycle base. There are several process to wirte test patterns for the tester to test the chip:
- ATPG (the test patterns are automatically generated by aptg tool)
- Dump files (VCD/EVCD) from functional simulation, required some tools to convert the files to...
Re: 4W on Lockup cells ?
Yes, we usually insert lockup latch in scan chain, especially those chains with cross clock domain, to avoid hold time violation.
If the same scan chain clock by the same clock source, usually we will insert buffers/inverters to fix the hold time problem.
scan flip flops
Normal Flip-Flop have D, Clk & Q.
Scan flop have D, SI (scan in), SE (scan enable), Clk, Q and/or SO (scan out).
During scan shift operation (SE=1), data will shift in through the SI pin.
Durig scan capture state (SE=0), data will capture into the scan flop via D pin.
I'm running physical optimization for my design using physical compiler.
Pls advice what is the best way to constraint the timing for all the scan in & scan out ports.
Here are some option i can think of but don't know which one is better, or whether there are other appropraite way to constraint...
test mode STA
hi,
Please advice how to constraint the chip timing, operating condition, loads etc., when we want to perform scan mode STA?
Any sample scripts available?
Thanks?
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