How can i make one standard cell delay zero in my design

[wein]

How can i only one standar cell in my design, when i read sdf ?

 

[zyphor]

Re: How can i make one standard cell delay zero in my desig

you can change the .v file for standcell , for example tsmc18.v

 

[haosg]

Re: How can i make one standard cell delay zero in my desig

yes, if no delay defined in library model file, the no annotattion occured.

 

[ken_ooi]

Re: How can i make one standard cell delay zero in my desig

can set delay_mode_zero if you use Ncsim

 

[sunspot]

If you run simulation, you can control the option of simulator.
If you run STA, you can modify the standard library and SDF file