Timing constraint for scan pins

[ken_ooi]

I'm running physical optimization for my design using physical compiler.
Pls advice what is the best way to constraint the timing for all the scan in & scan out ports.
Here are some option i can think of but don't know which one is better, or whether there are other appropraite way to constraint scan pin timing?
1) set multicycle path on all the scan in pins
2) no timing constraint for the scan in and scan out pins

 

[funzero]

when you do STA, you disable scan path by command like set_constant_for_timing

 

[yuzhicai]

use set_case_analysis on scan pad

 

[atremp]

Hi:

The scan in /scan out pins can be the dedicated test pin or shared with other input/output pins. As you know, in test mode we usually use the test clock which
is a low frequency clock(normally 10M clock). So in test mode, we care the hold timing more, if there are some setup violations, we just lower the frequency of test clock to resolve them. According to above, we use the functional constraint in shared scan input/output pins during synthesis process since that the function clock is more critical than test clock. And using the "set_case_analysis " command in STA process.

 

[eixeix]

Usually in scan test, clock is running at a lower frequency. In STA, you can use case analysis to check timing at functional mode and test mode with different timing constraints. Ignore timing on scan path is dangerous.