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Recent content by karthik87

  1. K

    Uart BFM --------(Bus function module)-*

    pl provide me the the solution of above asked question....ASAP
  2. K

    Uart BFM --------(Bus function module)-*

    Im using verilog language
  3. K

    Uart BFM --------(Bus function module)-*

    Hi i am writing code for UART BFM...can anyone pl help me regarding this..what tasks i have to write and which variables i should consider in the state machines pl reply ASAP..
  4. K

    Uart BFM --------(Bus function module)

    Hi i am writing code for UART BFM...can anyone pl help me regarding this..what tasks i have to write and which variables i should consider in the state machines pl reply ASAP...
  5. K

    Uart BFM -- (Bus function module)

    can u give more detail on uart BFM,what are the tasks involved in it....pl explain in brief..?
  6. K

    Uart Rx controller state machine

    Hi i have attached my incomplete Uart Receiver controller code.. My specification.... is Rx clock is 16times faster,i have to sample one data at 16clocks,then the data has to be given to shift register,after i receive stop bit i have to check for frame,overrun and parity errors and then send...
  7. K

    Uart BFM -- (Bus function module)

    Uart BFM -- (Bus function model) Hi everyone I want to prepare a uart BFM document and code for it, which consists of Tx and Rx How to start with it.....wat are the registers required..?how many tasks are required....?do i require a state machine...? and also if anyone has a reference...
  8. K

    UART RECEIVER Controller

    Hi Im writing code for rx side of UART and im using clock which is 16 times faster than Tx side...do i require to sample it,if so how to do it....??? and also let me know how to check for frame,overrun and parity errors Thanks in advance
  9. K

    Baud rate generator programming

    Hi im writing verilog code for baud generator....data is 32bit wide and i want to sample 32 times per bit....how to start the code..... pl help....
  10. K

    asynchronous fifo designing

    Hi i am writing code for async fifo. I have two domains write n read,in write domain i have to check full flag n in read domain empty flag..... I have started code with write domain...I have done bin to gray conversion for writeptr at writeclk.....is it required again to convert writeptr to...
  11. K

    How to write and read from apb to register bank?

    then in one state i can check for reading and writing to register.....?? or do i have to do write in one state and read in another state....???
  12. K

    How to write and read from apb to register bank?

    hi im writng to and reading from apb to register bank(it consists of uart registers) Is it required to assert wr_en<=1 before compairing the address and writing the data into register and for reading also should i check rd_en <=1 first and then compare the address and then start reading...
  13. K

    Fifo depth and fifo pointers

    Hi I am using an asynchronous FIFO in my UART design and my data width is 32 bits wide.pl tel me how to calculate the width and depth of the FIFO Also pl explain me how the FULL and EMPTY conditions are met. as i am using two different clocks for writing and reading pl tel me how to synchronize...
  14. K

    Testbench n Test case

    ya tats true...im student n writing the test cases n testbench arch for the first time jus i want to know how to start the document,how it will be actually written n documented
  15. K

    Testbench n Test case

    I am doing UART project,using APB interface.I am done with design document and have to prepare testbench architecture document and test case document. If anyone can please help about this testbench and testcase documents,how to start the document and what all we need to include in this It...
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