Testbench n Test case

[karthik87]

I am doing UART project,using APB interface.I am done with design document and have to prepare testbench architecture document and test case document.

If anyone can please help about this testbench and testcase documents,how to start the document and what all we need to include in this

It would me more helpful if provided with an example document(pdf) related to this,so that i can prepare mine with this as the reference

pl reply to the thread as soon as possible

 

[amitjagtap]

The one who design the system know very well which test cases are required to test the system.............

 

[karthik87]

ya tats true...im student n writing the test cases n testbench arch for the first time

jus i want to know how to start the document,how it will be actually written n documented

 

[imbichie]

If you need to need to write data to any register or something, its better to read the data from a text file by using the read, readline, etc command, also you can write the output data in the in to a text file by using the write command.

---------- Post added at 09:52 ---------- Previous post was at 09:44 ----------

Hi friend,

This is a method to write the testbench for a decoder.

-------------------------- rtl ---------------------------

LIBRARY ieee;
use ieee.std_logic_1164.all;
ENTITY decoder IS
PORT ( ena : IN STD_LOGIC;
sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
x : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END decoder;
ARCHITECTURE generic_decoder OF decoder IS
BEGIN
PROCESS (ena, sel)
VARIABLE temp1 : STD_LOGIC_VECTOR (x'HIGH DOWNTO 0);
VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH;
BEGIN
temp1 := (OTHERS => '1');
temp2 := 0;
IF (ena='1') THEN
FOR i IN sel'RANGE LOOP -- sel range is 2 downto 0
IF (sel(i)='1') THEN -- Bin-to-Integer conversion
temp2:=2*temp2+1;
ELSE
temp2 := 2*temp2;
END IF;
END LOOP;
temp1(temp2):='0';
END IF;
x <= temp1;
END PROCESS;
END generic_decoder;

--------------------------------- Testbench ---------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
entity decoder_tb is
end decoder_tb;
architecture tb of decoder_tb is
component decoder is
PORT ( ena : IN STD_LOGIC;
sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
x : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
end component;
signal ena:STD_LOGIC;
signal sel:STD_LOGIC_VECTOR (2 DOWNTO 0);
signal x:STD_LOGIC_VECTOR (7 DOWNTO 0);
begin
m_r: decoder port map (ena,sel,x);
x_rrocess
begin
ena<='1';
sel<="100";
wait for 1 ns;
ena<='1';
sel<="111";
wait for 1 ns;
ena<='1';
sel<="110";
wait for 1 ns;
ena<='1';
sel<="001";
wait for 1 ns;
ena<='1';
sel<="000";
wait for 1 ns;
ena<='1';
sel<="101";
wait for 1 ns;
ena<='0';
sel<="010";
wait for 1 ns;
ena<='1';
sel<="011";
wait for 1 ns;
ena<='0';
sel<="100";
wait for 1 ns;
ena<='1';
sel<="110";
wait for 1 ns;
ena<='1';
sel<="100";
wait for 1 ns;
ena<='1';
sel<="010";
wait for 1 ns;
wait;
end process;
end tb;