Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by karikalan_t79

  1. K

    How to debug synthesis error in Verilog

    only post map timing simulation will give you the idea
  2. K

    generating exponentials in vhdl

    vhdl exponent use function in vhdl or search for one google
  3. K

    How to implement filters on FPGA?

    Re: filters on FPGA system generator or some fir filter free tool, and dsp builder and fda in matalb
  4. K

    VHDL function to convert an vector datatype to integer

    vhdl conv_signed ya, use nuemric_std or synopsys lib is good for this conversions
  5. K

    free high level synthesizers (systemc)

    there is no free convertor at this time
  6. K

    10% Duty Cycle in VHDL

    duty-cycle vhdl use dcm or pll to get the duty cycle change
  7. K

    modelSIM question about VHDL to schematic

    gate level, if you target for fpga , you can see technology map of the rtl view otherwise if you go for asic, then target techology in particular synthesis tool
  8. K

    VHDL Code Error.Please Help.Urgent.

    declare constant in architecture part or in the pacakage of the design
  9. K

    Help me design a LVDS receiver

    Re: LVDS Receiver. lvds reference design in teh xilinx web for video application
  10. K

    any instruction for delay

    use a counter to generate the dealy,
  11. K

    what can I learn that get a good job?

    hard work and practise makes perfect dont worry
  12. K

    Video controller IP and PowerPC 405

    fpga powerpc std_logic pix col and row is need in order to track which line is scan by sync generator, and keep alling with the sdram
  13. K

    Making an IDE to Flash memory interface

    Re: IDE to Flash memory xilinx ref. design in spartan nand flash interface
  14. K

    How to learn Verilog for FPGA coding?

    Re: fpga coding synthesis guide in xilinx, altera ,mentor helps you to practise
  15. K

    "wait for" statement inside process with a sensiti

    Re: "wait for" statement inside process with a sen if you need delay, best use multiple dff in seiral fasihon to achive the same
See more

Part and Inventory Search

Back
Top