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Re: how to fix setup time violation after synthesis, don't lower the operating freque
Well, if you do not want to change the device, then you can apply forward bias on the Body/substrate terminal of the transistor.
The capacitance is actually inversely proportional to the oxide thickness. C= ξA/d where d= distance between the plates. So, as the thickness of oxide goes on decreasing, the distance between the gate and substrate reduces and cap goes up.
In the SPICE models of transistors, what is the parameter which when set can acknowledge the self heating effect. I am aware of SHMOD. Are there anymore flags/parameters that need to be set/reset to see the self heating effects on the FET performance.
could you elaborate. I will tell you the problem I am facing.
I want to implement the right shift on a register with data- in input. So, I have to define that register as inout. When I define it as reg, the problem starts....
I have a question for you shitansh.
I ma getting the error of "(vlog-2110) illegal reference to net" for a inout variable. Is it that we cannot declare a inout as a reg type?
Re: VHDL Programming
I have defined aclock input for every component, but how do i connect the clk. could u elaborate please. do i need to define the variable clk in the main program as global. how to do it?
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please can you suggest how in VHDL I can define a variable which is visible in multiple processes of different components,, for example, I need a common CLK
please can you suggest how in VHDL I can define a variable which is visible in multiple processes of different components,, for example, I need a common CLK
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