Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by karalamoorthy_p

  1. K

    [Moved]Arbitration and round robin process

    Hi All, I have four slaves like a,b,c,d. Here I am giving the priority to b,Once b is completed, then which slave it will take.(c or it will take any channels other than b) Please clarify this doubt. Difference b/w round robin and arbitration? Thanks
  2. K

    Parameterized interface in uvm

    Hi, Shall we use parameterized interface in UVM. Actually I want to use parameterized interface in uvm top. I am trying to use this way, but it's not working properly. In top module I am instantiating interface like this, a = 3; b = 1; para_interface #(.A(a),.B(b)) para_if()...
  3. K

    Clarification about Linting checks

    Hi, What is Linting and what is the use of linting ?. Why do we need linting checks? Suppose if we didn't do linting checks in RTL, what will happen? Please guide me.... Thanks
  4. K

    How to disable the fork join for this scenerio

    Hi fork task A; task B; task C; join $display("Fork-join is completed") Usually in the above cases the display is printed after all the tasks are completed. But in my case, two tasks are completed but one of the task is running infinite.How can I come out the fork join...
  5. K

    Difference between queue and mailbox

    Hi All, I have attended lot of interviews one moth back. All the interviewers asked this question. But I don't know the exact answer. If any one knows please reply back. Thanks and Regards, Karalamoorthy
  6. K

    Why we cant use always inside the program block

    Hi All, Why we cant use always inside the program block. Suppose if we use what will happen. suppose if we use forever what will happen. It is basic concept only, but I wanna know this things. Please reply back ASP. It would be helpful to me. Thanks and Regards, Karalamoorthy
  7. K

    What is the importance of assertion in verification

    Thank you so much Dave.
  8. K

    What is the importance of assertion in verification

    Hi All, I am new in SVA. Please I want exact usage of assertions. Because in all materials having explain like this, assertions are mainly used to test the behavior of the design. But in verification, we have added lot of checks to find the bugs. Then why we have to use assertion...
  9. K

    What is theuse of Dynamic casting($cast) in system verilog

    Hi all, I want to know about the use of $cast in system verilog. Because I didnt use this keyword till now. But in UVM I could see this keyword in all the class.So please explain the usage of $cast keyword with one simple example. If anyone knows please reply me. It would be greatful...
  10. K

    How to set the environment for gate level simulation

    Hi all, I am new in gate level simulation.Please could you tell me how to set up the Gate level simulation.Is there any guide or notes to refer the gate level simulation. Please help me to further. Thanks, Karalamoorthy
See more

Part and Inventory Search

Back
Top