Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: Layout problem
there is a DRC rule that poly should be enclosed by a pp layer for P-channel and with NP layer for n-channel transistor with a certain distance,which varies acc to technology...
what i think is that no. of multipiers are given by designer only...and regarding fingers;if it very very critical ckt.then we hav to consult it with designer that whether we can change it or not...and if it is not critical then we do it according to the space constraints...and according to the...
Re: Impedense matching
yup,this is a headache of designers only..as we do impedence matching for maximum power transfer..and so that reflections will be reduced..
Re: CMOS question?
if we are using 90 nm technology,it means minimum length of channel is 90nm.but it is always recommended to use length more then this..
Re: Wipro
i am working in wipro,bangalore.wipro pays different packages to different college graduates.so it depends on your package that how much u will get in hand.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
