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Re: does charge sharing in a Charge pump affects the PLL jit
In Razavi's text book, Analog circuit design (or else?)
there exists one chapter describing the topic
you can check that.
BRs
Re: question on ADC
hi all
Thanks for your suggestions.
First of all, this is the simulation result and the input range is from 0.5v to 1.5v for 1V ADC input.
The original designer set the ideal reference voltages and the result is somewhat better.
However, in my simulation condition, I use...
hi all
I input a very slow ramp to an 8-b ADC and got some strange output codes like
... 7 8 9 8 9 8 9 a 9 a b c ...
Is it because the input ramp voltage very close to comparator's ref or something else?
under this results, could we still say the ADC is monotonic?
Could anyone give me some...
hi
you can run .tran and sweep the control voltage.
And then use .meas to calculate the frequencies.
finally show the result within awaves with setting x-ray the "control voltage"
Hi all,
I have one question that while I set PFD input frequency high enough then the vco controlled voltage will oscillate. Could anyone explain it? And how to decide the PFD input range? Thanks so much!
have you checked your regulator's current supplied?
if the regulator cannot support enough current, it might cause the VDD noisy and this might be the reason I guess.
verilog-A is useful in co-simulation.
after co-simulation, you should replace the verilog-A with a real analog block.
so it's used to verify the analog block spec, not for synthesizing.
Added after 57 seconds:
verilog-A is useful in co-simulation.
after co-simulation, you should replace the...
Re: Question about buffer
hi,
about the gain-bandwidth vs Slew-rate relationship, you can simply see it as
the dc gain of the buffer Av=Gm*Rout and the dominate pole=1/(Rout*Cload)
the gain-bandwidth product equals Av times pole, such GBW=(Gm*Rout)*1/(Rout*Cload) = Gm/Cload = Gm*SR/I
then as...
Re: Ring Oscillator
As my experience, the regulator might help to reduce the vdd violation effect.
But how about the process violations and temp drift?
they're also problems to osc design.
Added after 23 minutes:
As my experience, the regulator might help to reduce the vdd violation...
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