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Hi Steve,
No, I could not find any official SPICE models so had to create my own based on the charts in the datasheet. If you have web links to the official models I would not mind downloading the official models so i can double-check against my models.
Thanks,
/John.
I have been searching high and low after a SPICE model for X2Y decoupling capacitors. I'm doing power integrity simulations in Hyperlynx and I need either SPICE or Touchstone (S-Parameter) models. Google gives me lots of PDF references that describe the SPICE schematics but I have no idea of how...
I have a prototype board that uses a DDR2 SO-DIMM. Due to a design error, the DQS6 and DQS7 pairs are swapped. Would the design still work?
The DDR2 interface is very slow on this board and all 64 bits are written and read at the same time by my custom logic. This should have the effect that...
I'm researching ideal PCB material for my 5 Gbps PCI Express design which uses RoHS parts. I want to create a very good PCB from a signal-integrity standpoint as well as reliability standpoint.
What PCB materials do you recommend and why?
This is for an 8-layer PCB with blind vias (780 pin BGA).
Measure the voltage difference on a low I/O pin in relation to the GND plane. If you are using a CPLD/FPGA then drive one of the I/Os low, make as many I/Os as possible go from low-to-high and measure the bounce on the I/O pin driven low. Due to inductance in the package leads you'll end up with...
Thanks. I ended up not needing to swap since I opted to use serial termination built into my FPGA (slow 200 MHz DDR2 interface). The few remaining pull-ups were pin swapped manually.
I'm working on a DDR2 interface which requires lots of pull-up resistors. My design uses x8 resistor arrays. In order to minimize trace stub lengths I would like to be able to utilize pin-swapping between the resistor arrays such that, after having been placed on the PCB, the resistor array pins...
Thanks Marce. I opted to use blind vias routed out on four signal layers. My PCB manufacturer has this capability. I don't have the PCB real-estate to route out in fewer layers. I ended up manually escape routing the signals - this actually was quite straight-forward.
I'm attempting to use the Autorouter in Altium Designer to simplify with the fan-out and escape routing of my 780-pin FPGA (8-layer PCB). I have found that the fan-out vias placed by the Situs autorouter are all full-stack vias although both blind and buried vias are defined too (via layer-pairs...
Apparently, Altium uses an internal database to keep track of the FPGAs that can be used with Altium Designer. It appears it is not possible to create a new FPGA schematic symbol/footprint from scratch that can be used as a "full" FPGA component for purposes of FPGA/PCB synchronization. I was...
I'm working on an 8-layer PCB design where an Altera Arria II GX is hooked up to a DDR2 SO-DIMM. I'm using Altium Designer Summer 09. Due to the large number of signals and layers I would like to set up my PCB project to use the pin swapping and FPGA/PCB pin synchronization feature built into...
I need to import my Altera Arria II GX IBIS simulation model into Altium Designer (Summer 09). Altium Designer however only appears to understand IBIS 3.2 since the import fails.
Is there a utility for converting an IBIS 4.1 format to 3.2?
Problem solved: I successfully imported the EP2AGX45.olb cadence schematic symbols I downloaded from Altera's site. The trick was to 'open' the cadence schematic symbol via ADs File/Open menu. This spawned the import wizard. I then generated the footprint using the IPC Wizard.
For some reason...
I need to create Altera Arria II GX 780pin footprint and schematic symbols for Altium Designer. I have found the below Mentor and Cadence libraries but I'm unable to import with Altium Designer (Summer 09). I'm using the Import Wizard but none of the files can be recognized.
Any help is...
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