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Hi
If you want to have IC layout from transistor schematic it is more practical than direct from Verilog to Transistor layout.
Tools starting from verilog (RTL, Behavioral, ...) result in gate level logic using sea-of-gates and standard cells.
If you want study on schematic to layout...
Hi
modelsim is the defacto of HDL world. Good and easy usage, fine waveform viewer and popularity.
it also in main stream of tools for mentor graphics. for example mentor Questasim is for verification.
tnx
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