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Hello,
I have two graphs which I have plotted in excel. I would like to place these graphs side by side and then export them both as ONE figure. Note I do not want to combine these two graphs into one!!
Does anyone know the best and easiest software to do this? I've tried with photoshop and...
lumerical
Hello all,
Has anyone every used Lumerical in the THz range? I know it's very commonly used for the visible range of the EM spectrum however I am unable to find any papers or documents relating to the use of Lumerical in the THz region.
Thanks,
Re: Why Silicon?
It depends on how many metal layers there are. Simply put more metal layers means several more processing procedures implying much more cost.
As an example a typical 4 metal layer Si CMOS process will cost around 15000 euros for 30-40 chips of ~ 6 mm by 6 mm.
It depends on how accurately you would like to sense the temperature and also what temperature range you are interested in. The other posters in this thread have suggested some good ideas (I myself use a PTAT temperature sensor).
Hi All.
Yesterday a colleague told me a thin oxide layer is present on his CMOS chip. I always thought the final passivation layer of any CMOS chip was Silicon nitride however this colleague says that a thin layer of oxide grows on top of this Nitride layer. Can anyone on the EDA board verify...
So it is possible to operate a CMOS chip that say has standard voltage ranges of 0-3.3 V (a la the AMS 0.35 um process), with an abnormal/unusual voltage range of -1.65V to +1. 65 V on the proviso that the p-type substrate is tied to the lowest postential (i.e. - 1.65 V)?
Many thanks to all!
Hello.
I may have posted this in the incorrect forum so apologies if this is so.
I'd like to canvas people's opinions on what DIP package is best to use. My CMOS IC will be 5 mm of 5 mm in size onto which I will have some basic microfluidics. I plan on using a DIP package for this chip and was...
Thanks for your comments.
Dual power supplies are only slightly more expensive than single polarity ones so I do not think this is the reason. I was thinking that there must be a technoloyical reason why -ve voltages in CMOS IC design are rarely used however after numerous google searches I've...
Hello.
Can someone please explain to me why negative voltages are not commonly used with CMOS IC chips? Why is the technology always described as being 0-3.3 V or 0-5 V for example?
I ask because my colleague has found a topology which is for a 0.35 um process that works for -1.5 V to 1.5 V...
conservative moderate liberal spectre
I don't think he has a problem with getting the oscillator to actually oscillate. The issue is speeding up the simulation, i.e. setting a larger step size between simulation points.
Does anyone else have any other ideas on how to speed up simulations in...
Hello all.
I have two lateral pnp transistors contained within one well. They are diode connected (i.e. the base and collectors are connected together). When I run ASSURA DRC I get the following error:
2 bad_n_well_welltap_multconn_erc
and the two base contacts of the lat 2 transistors are...
Hello all.
When I run ASSURA DRC on my layout I'm told there is one "DataAuditErrors". The area highlighted in my layout that is the cause of this error is a ring substrate contact (I have this for no other purpose other than as a contact for electrochemical etching. i.e. it serves no purpose...
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