Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
worst case analysis phase margin
Hi, when designing an LDO,is 20° phase margin enough for the whole loop?
I know that a stable loop need 45°-60° phase margin,but it seams that it's not so easy to improve the phase margin.
Regards.
jefferson
From China
Hi,polymath.I think it's not important if we show our country on the profile or the left of the posting.It doesn't mean that we are not proudy to be Chinese.What make sence is that we come from all over the world,EDAboard gives us a chance to know each other,we should learn to and...
The loop gain simulated is really above 60 dB(maybe infact it doesn't reach this number?).I can't see if there is a voltage difference at the opamp terminals.
You mean headroom problem?I think headroom problem is about dropout voltage.Even if the Vin is high,line regulation is no good.
A...
error amplifier op amp regulation
Hi,every.
You know that a LDO need an error amplifier(EA) to rgulate the Vout, the DC gain of EA and its bandwidth influence the line regulation and load regulation and PSRR and so on.
My LDO use an EA whose DC gain is about 60dB,UGB is 10M Hz. The whole loop...
It's not oscillation as I observed on the oscilloscope, the Vout voltage just decreases by about 30-40mV as Vin increases .The load regulation is no good too.
Bye the way,Vout is 1.8v, gain of EA is 65dB simulated.pass device is PMOS with W/L=35000.Vref is about 1V.
I think your equation is about LDO use bipolar device such as pnp transister as the pass element . Still I don't understand what does gmp*rop stand for.
I use a PMOS as the pass element,which I think the line regulation should be 1/[(Rds+Rl)*gm*A ]+ΔVref/(gm*ΔVin).isn't it? If calculated in this...
line regulation equation
TO SkyHigh:
Do you think how does the supply current influence the line regulation?
There isn't any inductive deices after the LDO except its pins. Caps used are all 1u ceramic caps.
bad line regulation
I'm sure bandgap is good.
But how can the Vout goes down when VDD increase? I can't understand.
Even if it is the reason of EA's offset,or channel length modulation,I think Vout should increase with VDD.
besides,the DC gain of the whole loop is about 70dB. maybe enough for...
Hi all,anyone know how to analysis the offset voltage of EA?
When simulated,it's seemed that little offset voltage exist.But infact it exists.
1.How to estimate it?
2.Is offset voltage varies with Vdd? How?
3.Is offset voltage has any relationship with its gain or bandwidth? How?
4.What would...
ldo line regulation
Hi all,
A problem I meet is that my LDO has a bad line regulation.
As Vin increases from 2.5V to 6V,Vout decreases by about 40mV,too big,Ithink.
Is the duty of error amplifier's offset voltage?
for it's already a chip,I can't measure the +/- point of EA.
Any reply would...
How about the drive capability of your output voltage?If you need high drive capability,a DC/DC or a charge pump would help you.But I think it's a hard work for a DC/DC to do the job.
gszczesz is right. poles induced by opamp is non-dominant pole,it's located at high frenquce point.waht we care about is the dominant pole whicth is critical to the stability of the whole systerm.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
