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Recent content by jducluzeau

  1. J

    I am trying to synthesize a code in xilinx ISE 9.2i .I am getting the following error

    Delays will not be synthesized.
  2. J

    verilog coding problem.

    IS there a difference with your previous post?
  3. J

    scanning flip flops with reset pins

    Kicchu, There is no problem to insert scan on flip flop with reset pins. You just need to control your reset path that's why no flip flop on reset path must be scanable. What your books want to say, you don't have scan flip flop which control synchronized reset or clock gating. For example, for...
  4. J

    Reading OUT ports for debugging

    then the problem is simple. you must use intermediate signals like this fifo1 :fifo(...,DOUT=>dout_int;....); DBG_FIFO_OUT <= dout_int; DOUT<=dout_int; In vhdl the only way you can use an output port is at left hand of an assignement. Regards, Jerome
  5. J

    Reading OUT ports for debugging

    Is DOUT an output port of this other module too?
  6. J

    Reading OUT ports for debugging

    where do you add these assignement? Inside the architecture of FIFO? Regards, Jerome
  7. J

    reading binary files in VHDL

    Concerning simulation, you can load file directly under your simulator I don(t remember the exact syntax but under modelsim it is something like this : load path/ram file_name Regards, Jerome
  8. J

    how to generate test pattern atpg in tetramax

    ok! you want to use Tetramax to generate ATPG patterns. But do you know what does these patterns?
  9. J

    how to generate test pattern atpg in tetramax

    There is no Flip flop in your code. This is only combinatorial. To generate ATPG patterns you need at least two Flip Flop, one scan_en input too.
  10. J

    RTL Source Compatibilty across the different make FPGAs

    if your design contains some RAMs. I'm afraid RTL can't be totally independant because each vendors have their own RAMs. But it is not a big work to change the instantiation of RAMs in the RTL.
  11. J

    how to generate test pattern atpg in tetramax

    you must have a gate netlist to generate ATPG patterns. Currently, Tetramax reads your code and doesn't see any scan Flip Flop then it generates nothing. Regards, Jerome
  12. J

    Declaration of signals in package

    why do you want to this? a signal represents a net or a port then. it is unique.
  13. J

    Finding Critical path using ModelSim

    The only I know to apply some timing to gate simulation (according gate are the results of synthesis) is to back-annotate your netlist from sdf file (maybe some other file exists). When you talked critical delay, you talked critical path? During your course you should learn timing path are the...
  14. J

    Finding Critical path using ModelSim

    Usually, for gale level simulation you use sdf file to define your delay and other timing. Timing inside sdf file are generated from your technolgy library and in real life all gate are not the same delay. Then I don't know the interest to want the same delay. Regards, Jerome
  15. J

    How to know whether a design is RTL or GATE

    Hi, RTL is your code you write in verilog or VHDL. Gate is the netlist after synthesis. We talked about netlist too. It is easy to see the difference. In netlist, there is no loop, no if. The tool which synthesize translate the RTL code in netlist to map sone primitive instances like...
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