Finding Critical path using ModelSim

[deepa1206]

Hi

Can anyone please tell me if it is possible to find critical path of a circuit using only ModelSIM?
Are there any commands/menu options available for that? I searched the internet and could not find any info.

Thanks

 

[xman24]

I don't think its there in modelsim! But you can get it from Design Compiler (Synopsys).

 

[rca]

you could but, you might generate some much patterns to be able to identify the right one that's could stimulate the critical path. Any synthesis tool will bring you the critical path.

 

[Rogov]

1. Synthesis determines whether you have critical path and what is it (start -> end)
2. With aid of Modelsim you can look through DataFlow to find specific information about this path.

 

[deepa1206]

Can I specify my own delays for gates in a synthesis tool?
Just for the simplification, I want to make delays of all gates=5ns.

Currently I have in my code

#5 a=~b;
#5 a= ~(b & c );

Synthesis will ignore the delays. How can I make synthesis tools use the gate delays that I want?

 

[jducluzeau]

Usually, for gale level simulation you use sdf file to define your delay and other timing.
Timing inside sdf file are generated from your technolgy library and in real life all gate are not the same delay.
Then I don't know the interest to want the same delay.


Regards,
Jerome

 

[Rogov]

For what are you using these delays?
You describe your device operation by this? Then it will be not synthesisable RTL-model. And you can not get the real implementation of this model.
If you wanna get real device you should use counters for this purpose.

 

[deepa1206]

I am a student and I was recently introduced to the concept of critical delays in circuit. We were given some circuits in the classroom and explained the concepts of false paths and told why critical delay is just not the sum of individual gate delays. I just wanted to know if we could find this by simulation. The examples I mentioned above (equal delays for gates, etc) are just for my understanding. I want to specify my own delays for the gates in the circuit.

 

[jducluzeau]

The only I know to apply some timing to gate simulation (according gate are the results of synthesis) is to back-annotate your netlist from sdf file (maybe some other file exists).

When you talked critical delay, you talked critical path?
During your course you should learn timing path are the result of gate delay, net delay, clock skew maybe. To have a net delay means the place and route has been done too.

At each stage of this flow, synthesis,place and route the tool used can give you a report for critical path.
It has more sense to define critical path with STA tools like PrimeTime than Modelsim.

I guess for a very small design you can see visually the critical path with modelsim but with a real design you can't there is too many path to check.

Regards
JErome