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I know that port is used to call a function(task) and imp define the implementation of that function(task)
So a port to imp connection is made (for example driver sequencer communication)
Can anybody give me idea and example when we need to use export
Thanks in advance.
This may be a silly question.
I am wondering why we can not connect driver and sequencer with out port, to implement get_next_item and item_done.
Like,
driver.connect(sequencer)
function connect(uvm_component m_comp);
m_comp = sequencer
endfunction
while we call
driver.get_next_item();
it...
What is difference between below two code execution
Code 1:
class_p p1,p2;
p1 = new();
p2 = new();
p2 = p1;
Code 2:
class_p p1,p2;
p1 = new();
p2 = new p1;
What is difference between above two. I understand both are same. (like, p2 = new p1; would in turn do p2 = new; p2 = p1;)
But it is...
I come across the term far end receiver termination with differential signal very often. Can anybody explain what is far end receiver termination and how it is detected in simple terms
Thanks for reply.
My question is different.
in base.copy(this); I assign value to variable A for object base. But base object is of type base_class.
base_class do not have variable A.
Here I have tried to mimic clone method of uvm_object.
typedef base_class;
typedef derived_class;
function base_class create();
derived_class tmp;
tmp = new();
return tmp;
endfunction
class base_class;
virtual function do_copy(base_class rhs);
endfunction
virtual function...
In below code a class is having object of itself. Object of own type is created before class definition completes (before endclass.)
This is working. Compiler do not give any error. Can anyone explain me how this works?
class test;
test self;
function create_me();
self = new()...
class Base;
rand integer vari;
constraint range { 0< vari < 100 ;}
endclass
module test;
Base objh =new();
initial
begin
if(objh.randomize())
begin
$display(" Randomization is done ");
end
$display(" objh.baseh.vari : %d ", objh.vari );
end
endmodule
Output : objh.vari : 1245020823
My...
When we call new constructor for derived class, system verilog will call new for base class automatically. Memory for base class will be automatically created. Derived class can not be created with out creating parent class.
"A super.new call shall be the first statement executed in the...
Hi Dave,
I have following queries. It will be very helpful if you can answer inline.
1. Function or task with automatic lifetime, will create multiple call memory, if called at same time. yes or no
2. Function or task with static lifetime, will create single call memory, if called at same...
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