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assing some tepm register to store the previous data and compare it with new data as soon as u get the new data.... after comparing, assign new data as temp data for next sample.
Re: vhdl testbench
First advice is use latest version of ispLEVER.. If I am not wrong its 5.0... older versions are not very efficient and there are few bugs....Precision is new in market but its good tool. Are you licence version of ispLever??
I think ispLever has GUI based simulations where...
Re: FPGA and CLK
No big deal...!!! you can use it if its connected to FPGA pin....if its not connected to global clock pin then the clock performacne (max frequency ans swek) may not be as ggod as GCLK pin. Alternative is use buffered clock and use it for all modules..
4 bit asynchronous counter verilog code
here it worked without any change because outputs will be registered and instance name will be taken by the tool automatically........
But obviously its not a good design practise......
affecting weak pull down in ise
if ur not using GUI Constraint editor then assign PULLUP or PULLDOWN in the .ucf file (constraint file) where u are assigning your signal to the pin.
If not clock then atleast there will be one common signal connected to both the blocks....and the STA tool will show that path... you may see that in the unconstraint path report...
But its advisable to connect external reset to the device if in case u want to put the device in to predefined state......
Is it OK if we float the reset pin of the FPGA ?
automatic traffic light
you shoul dhave sensors to detect traffics...?? what kind of design ur lookin for ?? controller based or FPGA/PLD based ? Do u have analog circuitry ready ?
it is based on which signals ur declaring in the process ( ) statement also... if ur logic is CLOCKed then u need to include only clock signal in the process list and the hardware will eb different...
Re: Lattice plsi5256
u can use ispVM software and ispVM parallel port cable to program it. You need to have JTAG connector on ur boad. Else you can use JTAG tool itslef to program he PLD. You can use .SVF (serial Vector Format) file to load it.
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