About sequentiality(?) of processes

[jedihe]

Hi, I was talking with a friend about VHDL, and he told me that inside a process, the operation is SEQUENTIAL, he showed me code like this:

process (...) 
begin
   signal <= "000";
   if clk'event then
      signal <= signal + 1;
   end if;
   if some_flag then
      signal <= 0;
   end if;
end process

The point is: he said the first line inside the process causes some kind of initialization, and then the others get executed... but for me that's not true: we are talking about HARDWARE, and once it gets synthesized, everything works as YOU define it. However, I have some doubt... is my position correct?

Thanks in advance!

jedihe

 

[sp]

i think wad ur fren mean is the IF statement...

whenever u use the IF statement, then there will b having the priority encoder used.... the first IF statement always hav the highest priority....

hope i am talking about hardware now....

my regards,
sp

 

[tkbits]

jedihe,

If we are talking about synthesis, you are correct.

Because <= is used, the first line in the process defines a DEFAULT, not an initialization. And the following lines with <= represent overriding definitions of the signal.

If := were used, logic would need to be created that generates a result equivalent to a sequential execution with delayed results.

As far as I know, asynchronous digital computers are still pretty much research objects. One must remember that conventional computer architecture is CLOCKED LOGIC. Software programming assumes this, even though the granularity of the clocking may be unknown or ignored.

If the process were truly executing sequentially, what is clocking it? And if the process were truly executing sequentially, you would get a signal glitch when the example signal is set to 0 at the beginning of the process.

Finally, as a counterexample to "it's sequential", the following code represents a shift register, not a bit propagator:

process (clk)
begin
  if rising_edge(clk) then
    s3 <= s4;
    s2 <= s3;
    s1 <= s2;
    s0 <= s1;
  end if;
end process;

 

[jedihe]

Thanks a lot, I will talk to him and tell you what happen...

jedihe

 

[jay_ec_engg]

it is based on which signals ur declaring in the process ( ) statement also... if ur logic is CLOCKed then u need to include only clock signal in the process list and the hardware will eb different...