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- check if the file you think is the sim input is the same as in Settings->Simulation Settings-> Simulation input
- change 'X' in the inputs to '1' or '0' in the input vwf file
- cyclone3 is not very fast device, make input levels stable longer than 10ns
j.
you have:
always @(/.../)
if
else
if
should be [depends on your intention]
always @(/.../)
begin
if
else
if
end
// --- or
always @(/.../)
if
else if
else
j.
the thread is about to be closed;
just few last notes;
sounds slightly beter then:
and much better then:
I was not going to argue what solution is the best;
there is no 'best' solution in all cases;
I was just 'triggered' by the statement:
Delaying 'wait' by clocking it will result in a...
always @(posedge av_clk)
if ( !(av_read || av_write) ) av_wait <= 1'b1;
else if (write_done || read_done ) av_wait <= 1'b0;
I don't think an async. control of 'av_wait' will work faster then the example above;
j.a
an Avalon slave can keep wait high 'by default' and drop wait low
when read data ready / write data written;
so wait can be registered :)
--------------
btw - the only 'ping-pong' term I've heard in fpga field is 'ping-pong buffers'
j.a
if you use quartus simulator there is on way to get 'X'
as you simulate netlist;
you can see 'X' in simulation only if you forget to add all input
signals to the waweform;
looks like you haven't set:
settings->simulator settings->simulator output files:
"overwrite simulation input file with...
at first change output leds to output reg [7:0] leds
and comment out 'reg [7:0] leds';
then read carefully compilation warnings;
check what leds[7:0] signal level, 'LOW' or "HIGH', switch your
board LEDs 'ON';
j.a
not exactly, as Tricky said - synchronize the reset and use it as async. input to registers;
the advantage of such approach is that the async. reset is an independent input to FPGA cell so
doesn't consume data inputs;
j.a
mod = a;
syntax error,
you can
assign mod = a;
or
1.always @(posedge clk) mod <= a;
2.always @(*) mod <= a;
but in these cases 'mod' has to be declared as reg
while (mod) begin
while can be used in always block
but in general - the code will not work, fpga is not a processor
which...
such example is compiled by quartus without warnings and [quartus] netlist simulation
shows possibility of writing on rising edge and then reading the same location
on falling clock edge;
module dual_edge_ram
(
input clk, wr,
input [7:0] addr_in, addr_out,
input [7:0]...
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