Modulus Module Needs Assistance

[zclimes]

Hello all. This is my first time posting to this forum, so be gentle. I am trying to write a module in Verilog, using Xilinx ISE 13.4, that takes two eight-bit numbers and outputs the modulus of them, mod = a % b. I know the modulus can easily be found by repeatedly by taking a - b, then that result - b until the result is smaller than b, and outputting the result as the modulus. However, I can't quite transfer that thought process into Verilog. I have a few lines of code that I think represent the correct general structure of the algorithm, but it won't compile.

Here's the code:

module modulus(
input  [7:0] a, 
input  [7:0] b,
output [7:0] mod
);

mod = a;

while (mod) begin
if(mod > b) begin
	mod = mod - b;
end
end
endmodule

and here's the error that it produces:
ERROR:HDLCompilers:26 - "modulus.v" line 29 expecting 'endmodule', found 'while'

Line 29 is where the while statement is. I don't understand why it's looking for an endmodule there either. I'm relatively new to Verilog, so I could just be making a really idiotic and obvious mistake, but I can't find it. I really appreciate any help on the issue.

 

[j_andr]

mod = a;
syntax error,
you can
assign mod = a;
or
1.always @(posedge clk) mod <= a;
2.always @(*) mod <= a;
but in these cases 'mod' has to be declared as reg


while (mod) begin

while can be used in always block


but in general - the code will not work, fpga is not a processor
which executes code line by line;

this is how it can be done from verilog syntax point, but will not do exactly
what you want:

// ... //
output reg [7:0] mode
);
 always @(posedge clk)
    begin 
      mod <= a;
      if(mod > b)
	    mod <= mod - b;
  end

j.a