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Recent content by it_boy

  1. I

    [SOLVED] verilog event disable

    @graphene: Thanks for your reply, I currently dont have clock or other signals that you have mentioned. Will try out your code sometime. @dave_59. Thanks a lot for the explanation. Understood the problem with my always statement. Your piece of code solved my problem. Will look for "Verilog...
  2. I

    [SOLVED] verilog event disable

    I am trying to generate a pulse at every rising edge of "inp" signal. I am using event to do the same. Problem occurs whenever event triggers during the delay of the pulse_width. Named block gets disabled, but never event does not trigger. Have a look at attached file to see what I mean. Can...
  3. I

    RS-232 Receiver and Transmitter Design in VHDL

    vhdl rs-232 have a look at this... **broken link removed**
  4. I

    Microcontroller FPGA for a beginner

    Microcontroller FPGA check Virtex-2 pro, virtex-4 and virtex-5 devices from xilinx
  5. I

    What is the difference between DLL and PLL?

    steve kilts check this out https://www.xilinx.com/support/documentation/application_notes/xapp132.pdf
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    Are there any FPGAs that support 1 gbps data rate?

    Re: clock in fpga If you want 1gbps serial data, you may have to use the Rocket-IO serdes present in Virtex family devices. With existing Spartan series, you will not be able to schieve Gbps rates.
  7. I

    Where do you from and how many languages speak?

    From India, Can speak Kannada, Tamil, Hindi, English
  8. I

    Single-Ended vs Differential [hlp]

    Usually the value of the differential signal depends on the difference in the amplitude between the two signals and the phase difference between them.
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    ISSUE WITH RESET SIGNAL PASSED TO CYPRESS CHIP FROM FPGA

    Could not understand you properly. but, have you checked if the reset at the output of the FPGA is getting asserted? Have you checked with an oscilloscope? How are you generating the reset in the FPGA? does it meet the minimum period required for CY7C68013?
  10. I

    CRC DECODER ENCODER WITH LFSR

    crc encoder Have a look at this... **broken link removed**
  11. I

    4*4 keypad and 20*4 LCD display

    have a look at the projects listed in www.opencores.org You will get an idea looking at the keypad and the LCD controller cores. You may have to customize for the LCD/Kaypad and the CPU you are planning to use.
  12. I

    How to implement SW_reset in Verilog?

    Re: SW_reset Are you planning to use this register (sw_reset) as a synchronous reset? If yes, then timing problems might occur depending on the delay on that line depending on the size of the FPGA, percentage of FPGA utilized and the routing for the reset path. I suggest you to use the...
  13. I

    Designing a battery charger to automatically switch over from 12V source to battery

    battery charger Time for charging the battery is not a real constraint. I cannot change the battert though. So, I am stuck with a 9.6V battery. Should I consider boosting the input from 12V tp 15 or 16V for charging the battery?
  14. I

    Designing a battery charger to automatically switch over from 12V source to battery

    Re: battery charger Thanks rogerynt. The battery charge controller MC33340 is supposed to do all the functions indicated by you. Unfortunately I found that it is not possible to charge a 9.6V battery from a 12V source with a switching regulator.
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    Designing a battery charger to automatically switch over from 12V source to battery

    Re: battery charger Thanks for the input. I was thinking if a mosfet would be better as a diode would drop around 0.7 to 1 volt which decreases the efficiency of the battery. What should be the charging voltage of a 9.6V NiMH battery?
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